DFT · Chapter 4 · Scan Insertion & DRC
Scan Stitching & Chain Ordering
Scan stitching is the tool step that connects scan cells into chains, wiring each cell's output to the next cell's scan input and assigning chains to scan pins, automating at scale what earlier chapters did by hand. Chain ordering is the sequence of flops within a chain, and the key insight is that any order shifts the same data, so ordering is functionally free but physically significant. Ordering flops by physical proximity, done as a reorder step after placement, keeps the scan route short and cuts wirelength and congestion. Ordering also affects shift-path timing: adjacent scan cells clocked almost together can let shift data race into the next cell, a hold violation especially across clock-skew or clock-domain boundaries. The fix is a lock-up latch, a level-sensitive latch that retimes the shift data by half a cycle. The flow is logical stitch, place, reorder for proximity, then insert lock-up latches at domain boundaries.
Intermediate13 min readDFTScan StitchingChain OrderingLock-Up LatchHold
Chapter 4 · Section 4.2 · Scan Insertion & DRC
Project thread — 3.6 hand-stitched the counter; this lesson is the automated stitch + ordering (with lock-up latches) that 4.5 applies to the FSM.
1. Why Should I Learn This?
Stitching and ordering turn scan cells into working, well-routed, hold-clean chains — the difference between scan that works and scan that fails integrity.
- Stitching: connect cells Q→SI into chains, assign scan pins (automates 3.6).
- Ordering is functionally free but physically significant — reorder by proximity after placement to cut wirelength.
- Shift-path hold races (adjacent cells clocked together, esp. across skew/domains) → fix with a lock-up latch (half-cycle retime).
- Flow: stitch → place → reorder → lock-up latches.
2. Real Silicon Story — the chain that failed integrity at a domain crossing
A design stitched a scan chain that crossed from one clock domain into another mid-chain (a common convenience). It passed simulation but failed the chain-integrity flush test intermittently on silicon — a known pattern shifted in didn't come out intact.
The cause was a shift-path hold race: at the domain crossing, the two adjacent scan cells were clocked with enough skew that the shift data raced through — the receiving cell captured the new value before it should, corrupting the shifted stream. It wasn't a defect; it was a timing race on the scan path.
The fix was a lock-up latch at the crossing — a level-sensitive latch that holds the shift data for half a cycle, so the receiving cell samples the stable value and the race disappears. The team didn't slow the shift clock everywhere (which would raise test time, 1.4) — they inserted a lock-up latch exactly where the crossing needed it. Lesson: shift-path hold across skew/domain boundaries is fixed by lock-up latches, not by punishing the whole chain's shift speed.
3. Factory Perspective — stitching/ordering through each lens
- What the test engineer sees: a stitching/scan-chain report (order, lock-up latches, pin map) and whether chain integrity passes — a hold race shows as flush failures.
- What the yield engineer sees: that chain-integrity fails from ordering/hold are a test-setup/timing issue to distinguish from real defects (uniform vs scattered, 3.3).
- What the RTL/DV / physical engineer sees: that chain order is a P&R optimization (proximity → wirelength) and that clock domains/skew dictate lock-up latch placement.
- What management cares about: that good ordering cuts routing/congestion (area/schedule) and that lock-up latches avoid slowing shift (test time, 1.4) — a PPA + test-cost win.
4. Concept — stitch, order, and lock-up latches
Scan stitching (automating 3.6):
- The tool connects each scan cell's Q to the next cell's SI, from a scan-in pin to a scan-out pin, forming the chains defined by the count/length/balance plan (3.5).
- It assigns scan pins and records the result in a scan chain / stitching report.
Chain ordering — functionally free, physically significant:
- Any order of flops shifts the same data (the chain is a shift register regardless of order) → functionally free.
- But the physical route threading Q→SI through the chain depends entirely on the order:
- Proximity order: short, low-congestion scan route.
- Arbitrary order: the scan wire snakes across the die → wirelength/congestion cost.
- So ordering is done as a post-placement reorder — an initial logical stitch, then reorder by physical proximity once placement is known (a standard P&R step). Reorder re-maps ATPG's chain bit positions (a minor recompute) for a big wirelength win.
Shift-path hold and lock-up latches:
- Adjacent scan cells are clocked ~simultaneously during shift → the shift data must arrive at the next cell after it has safely captured, i.e. it must meet hold.
- Across clock-skew or clock-domain boundaries, the clocks can be skewed enough that the data races through → hold violation → corrupted shift (the story).
- Lock-up latch: a level-sensitive latch inserted between the two cells that holds the shift data for half a clock cycle, so the receiving cell samples a stable value → the race is broken. It affects only the shift path, not the functional capture.
The order of operations:
- Logical stitch → placement → physical reorder (proximity) → lock-up latch insertion at skew/domain boundaries → final, DRC-checked chains (4.3).
5. Mental Model — routing a delivery run, with a relay handoff
Picture the scan chain as a delivery driver who must visit every house (flop) once, carrying a parcel house-to-house (Q→SI).
- Chain order = the visiting sequence. Visiting houses in a random order means driving back and forth across town (long wirelength). Visiting nearby houses in sequence (proximity reorder) means a short, efficient route — same houses, same parcels, far less driving.
- You plan the route after you know where the houses are (post-placement reorder), not before.
- At a district boundary where clocks tick slightly differently (skew/domain), a handoff can go wrong — the next driver grabs the parcel too early (a hold race). You add a relay runner who holds the parcel for a beat (a lock-up latch) so the handoff is clean.
- You don't make every driver slow down (slow the whole shift clock) to fix one bad handoff — you add a relay exactly at that boundary.
Same visits, same parcels — a smart route and a relay at the tricky handoff make it fast and reliable.
6. Working Example — reorder a chain, fix a hold race
Reorder for proximity, then break a boundary race with a lock-up latch:
# Chain ordering — REPRESENTATIVE, SIMPLIFIED, tool-neutral:
# Logical stitch (arbitrary): scan_in -> fA -> fZ -> fB -> fY -> scan_out (fA,fB near each other; fY,fZ far)
# -> scan route jumps across the die (long wirelength, congestion)
# Post-placement REORDER by proximity: scan_in -> fA -> fB -> fY -> fZ -> scan_out (visit near-neighbors in sequence)
# -> short scan route. SAME data shifts (order is functionally free); ATPG re-maps bit positions.# Shift-path hold race + lock-up latch — REPRESENTATIVE:
# Chain crosses clkA -> clkB with skew. Adjacent cells: cellA (clkA) -> cellB (clkB)
# Skew lets cellA's shifted Q reach cellB BEFORE cellB safely holds -> HOLD violation -> corrupted shift -> integrity FAIL
# FIX: insert a LOCK-UP LATCH (level-sensitive, clocked on the opposite phase) between cellA and cellB
# -> latch HOLDS the shift data half a cycle -> cellB samples a STABLE value -> race broken -> integrity PASS
# Do NOT slow the whole shift clock (raises test time, 1.4) -- fix the boundary locally with a lock-up latch.7. Industry Flow — stitch, place, reorder, lock-up
The stitching flow interleaves with placement and timing:
8. Debugging Session — chain integrity fails at a domain boundary
A scan chain that crosses a clock-domain boundary fails the chain-integrity flush test intermittently, and the team wants to slow the shift clock for the whole design; the real cause is a shift-path hold race at the boundary where adjacent scan cells are clocked with skew, and the targeted fix is a lock-up latch that retimes the shift data by half a cycle
SHIFT-PATH HOLD RACE → LOCK-UP LATCH, NOT A SLOWER WHOLE-CHAIN SHIFT CLOCKA scan chain that crosses a clock-domain (or high-skew) boundary fails the chain-integrity flush test — a known sequence shifted in doesn't come out intact, intermittently. The proposed fix is to slow the shift clock across the whole design.
Adjacent scan cells at the boundary are clocked with enough skew that the shift data races from one cell into the next before it safely captures — a hold violation on the shift path — so the shifted stream is corrupted, and slowing the global shift clock is an expensive, over-broad fix. During shift, every scan cell passes its value to the next cell on the same clock edge, so correct shifting depends on the receiving cell holding its previous value until it has captured — a hold requirement on the scan path between adjacent cells. Within one well-balanced clock domain this is usually fine, but at a clock-domain crossing (or a point of significant clock skew), the two adjacent cells' clock edges are offset: the launching cell's new value can arrive too early at the receiving cell, which then captures the new value instead of the old — corrupting the shift and failing chain integrity, and doing so intermittently because it depends on the exact skew and conditions. It is not a defect and not a reason to slow the entire shift clock — that would fix the boundary at the cost of longer shift time on every pattern (1.4), punishing the whole design for one local timing problem.
Insert a lock-up latch at the boundary to retime the shift data by half a cycle — a local, cheap fix that leaves the shift clock fast. A lock-up latch is a level-sensitive latch placed between the two adjacent scan cells at the skew/domain boundary; it is clocked on the opposite phase, so it holds the shift data for half a clock cycle before releasing it to the receiving cell. That half-cycle delay guarantees the receiving cell samples a stable, old value — the hold race is broken and chain integrity passes — while the shift clock stays fast everywhere else. Scan-insertion tools add lock-up latches automatically at detected crossings, but you must ensure clock-domain grouping and skew data are correct so they land where needed. The principle to lock in: scan stitching connects cells into chains and chain ordering is functionally free but physically significant — reorder by proximity after placement to cut wirelength — while adjacent scan cells clocked with skew (especially across clock domains) create shift-path hold races that corrupt shifting, and the correct fix is a lock-up latch that retimes the shift data by half a cycle at that boundary, not slowing the whole chain's shift clock. (Chain count/balance is 3.5; scan DRC that checks all this is 4.3; clock-domain handling detail is 4.4.)
9. Common Mistakes
- Ignoring chain order's physical cost. Arbitrary order snakes the scan route — reorder by proximity after placement.
- Reordering before placement. Proximity is only known post-placement — that's when to reorder.
- Slowing the whole shift clock to fix one race. Use a lock-up latch at the boundary — keep shift fast (1.4).
- Forgetting lock-up latches at domain/skew crossings. Shift-path hold races → integrity failures.
- Assuming order changes function. It doesn't — any order shifts the same data (ATPG just re-maps bits).
10. Industry Best Practices
- Reorder chains by physical proximity post-placement — minimize scan wirelength/congestion.
- Insert lock-up latches at clock-domain/skew boundaries — break shift-path hold races locally.
- Keep the shift clock fast — fix races with lock-ups, not global slowdowns (test time, 1.4).
- Group by clock domain and record it in the stitching report (with 3.5's balance).
- Verify chain integrity after stitching/reorder (3.3) — the ordering/lock-up check.
11. Senior Engineer Thinking
- Beginner: "Chain integrity fails at the domain crossing — slow the shift clock for the whole design."
- Senior: "That's a shift-path hold race at the skewed boundary — the receiving cell grabs the value too early. I insert a lock-up latch there to hold the data half a cycle, breaking the race locally, and keep the shift clock fast everywhere else. And I reorder by proximity so the scan route isn't snaking across the die."
The senior fixes boundary hold with a lock-up latch and optimizes order for routing, never punishing the whole chain.
12. Silicon Impact
Scan stitching and ordering are where scan's logical structure meets the physical die, and handling them well pays off in routing, timing, and reliable shift. The liberating fact is that chain order is functionally free — any order shifts the same data — which turns ordering into a pure optimization: reorder by proximity after placement and the scan route (a wire that threads through every flop in the chain) becomes short and low-congestion instead of snaking across the die. The subtler, higher-stakes issue is shift-path timing: because adjacent scan cells shift on the same edge, correct shifting depends on hold between them, and at clock-domain or high-skew boundaries that hold can be violated, producing chain-integrity failures that are intermittent and easily misdiagnosed as defects or as needing a slower shift clock. The right, standard fix — a lock-up latch that retimes the shift data by half a cycle — resolves the race locally while keeping the shift clock fast, protecting test time (1.4). Scan-insertion and P&R tools automate stitching, proximity reorder, and lock-up insertion, but they rely on correct clock-domain and skew information, so the DFT + physical engineer must ensure domains are grouped and boundaries are known. For the RTL/DV engineer, the connection is that your clock-domain structure (from scan-ready design, 4.1) determines where lock-up latches are needed, and the stitching report is where ordering, lock-ups, and pin mapping become visible — the concrete, at-scale realization of the hand-stitch you did on the counter in 3.6, and the input to the FSM insertion in 4.5.
13. Engineering Checklist
- Stitched scan cells into chains (Q→SI) per the count/balance plan (3.5).
- Reordered chains by physical proximity after placement (short scan route).
- Inserted lock-up latches at clock-domain/skew boundaries (shift-path hold).
- Kept the shift clock fast — no global slowdown to fix a local race.
- Verified chain integrity (3.3) and reviewed the stitching report (order, lock-ups, pins).
14. Try Yourself
- Given four flops with known placement, write an arbitrary stitch order and a proximity reorder — compare scan-route length.
- Confirm both orders shift the same data (functionally free) — note ATPG just re-maps bit positions.
- Build a chain crossing two clock domains; identify the adjacent cells at the boundary.
- Show a shift-path hold race there, then insert a lock-up latch and explain the half-cycle retime fix.
- Argue why a lock-up latch beats slowing the whole shift clock (test time, 1.4).
Reasoning is tool-neutral. Real stitching/reorder/lock-up insertion come from scan-insertion + P&R tools. No paid tool required to reason about ordering and hold.
15. Interview Perspective
- Weak: "Stitching connects the scan cells; order doesn't really matter."
- Good: "Stitching wires cells into chains; order is free functionally but affects routing, and lock-up latches fix hold at domain crossings."
- Senior: "Stitching connects scan cells Q→SI into chains and assigns scan pins — automating the hand-stitch. Chain order is functionally free (any order shifts the same data) but physically significant: I reorder by proximity after placement to keep the scan route short (wirelength/congestion). The timing catch is shift-path hold — adjacent cells shift on the same edge, so at clock-domain/skew boundaries the data can race into the next cell, failing chain integrity. The fix is a lock-up latch — a level-sensitive latch that holds the shift data half a cycle — inserted locally at the boundary, not slowing the whole shift clock (which would raise test time). Tools automate all of this given correct clock-domain/skew info."
16. Interview / Review Questions
17. Key Takeaways
- Scan stitching connects scan cells Q→SI into chains and assigns scan pins — the automated, at-scale version of the hand-stitch (3.6), following the count/length/balance plan (3.5).
- Chain ordering is functionally free (any order shifts the same data) but physically significant — reorder by proximity after placement to minimize scan-route wirelength/congestion (ATPG just re-maps bit positions).
- Shift-path hold races arise because adjacent scan cells shift on the same edge; at clock-domain/high-skew boundaries the data can race into the next cell → chain-integrity failures.
- The fix is a lock-up latch — a level-sensitive latch that retimes the shift data by half a cycle at the boundary — applied locally, not by slowing the whole shift clock (which raises test time, 1.4).
- The flow is logical stitch → place → reorder by proximity → insert lock-up latches → DRC-checked chains (4.3), and the stitching report records order, lock-ups, and pin mapping. Next: 4.3 — scan design-rule checking (DRC).
18. Quick Revision
Scan stitching & chain ordering. STITCH = connect scan cells Q→SI into chains + assign scan pins (automates 3.6). ORDER = functionally FREE (any order shifts the same data) but physically SIGNIFICANT → reorder by PROXIMITY after placement to cut scan-route wirelength (ATPG re-maps bits). Shift-path HOLD race: adjacent cells shift on the same edge; at clock-domain/skew boundaries data RACES into the next cell → chain-integrity FAIL. Fix = LOCK-UP LATCH (level-sensitive latch, half-cycle retime) at the boundary — LOCAL fix, keep shift clock FAST (don't slow the whole chain — test time, 1.4). Flow: stitch → place → reorder → lock-up latches → DRC (4.3). Next: 4.3 — scan DRC.