Scan Chains: Shift In, Capture, Shift Out

Chapter 3 · Section 3.3 · Scan Architecture

Project thread — 3.2 made a single scan cell; here we chain cells and run the shift-in / capture / shift-out cycle. 3.6 runs this exact cycle on the counter to detect a fault.

1. Why Should I Learn This?

The shift-in → capture → shift-out cycle is the operating procedure behind every scan-based ATPG pattern and tester program.

• Chain: scan cells wired Q → next SI, from a scan-in pin to a scan-out pin.
• Shift in (SE=1): N clocks load a stimulus into all flops (controllability).
• Capture (SE=0): one functional clock — combinational logic responds, result captured.
• Shift out (SE=1): N clocks unload the response (overlapped with the next shift-in); tester compares to golden.

2. Real Silicon Story — the coverage that was built on a dead chain

A team generated thousands of scan patterns and reported high coverage in simulation — then the silicon failed everything on the tester. Panic: a catastrophic yield problem?

No. A single scan cell in one chain had a defect that broke the shift path — the chain couldn't shift a known value end to end. Every pattern's scan-out was garbage, so every compare failed. The elaborate coverage meant nothing, because the chain itself didn't work — you can't load or observe state through a broken shift register.

The fix wasn't in the patterns — it was to run a chain-integrity (flush) test first: shift a simple 0011... sequence through each chain and confirm it emerges intact. That would have caught the dead chain immediately. Lesson: chain integrity is a precondition for all scan test — prove the chains shift correctly before you trust a single coverage number.

3. Factory Perspective — the scan cycle through each lens

• What the test engineer sees: the tester program driving SE and clocks through shift-in / capture / shift-out, plus a chain-integrity test that must pass first.
• What the yield engineer sees: chain-integrity fails vs logic (capture) fails — a dead chain is a different diagnosis (often a scan-path defect) from a scattered logic fault.
• What the RTL/DV engineer sees: that shift length = flop count, so their flop count drives shift cycles (test time, 1.4) — and that clean synchronous design keeps chains shiftable.
• What management cares about: shift cycles × patterns is the test-time cost (1.4); it's why compression (Ch7) is funded — and why chain-integrity discipline avoids false yield scares.

4. Concept — the chain and the three-phase cycle

The scan chain:

• Scan cells connected Q → SI in series, from a scan-in pin (head) to a scan-out pin (tail).
• In shift mode (SE=1) the chain is a shift register; in capture mode (SE=0) each cell captures its functional D.
• Chain length N = number of flops in the chain = shift cycles per load/unload.

The fundamental test cycle:

1. Shift In (SE=1): clock N times to serially load the stimulus pattern into all flops. Now every flop holds a chosen value → full controllability.
2. Capture (SE=0): apply one functional clock. The combinational logic between flops computes on the loaded state (and any primary inputs), and the results are captured into the flops. (At-speed capture uses rated-clock timing — 2.3, 3.4.)
3. Shift Out (SE=1): clock N times to serially unload the captured response to scan-out — while shifting in the next pattern (the two overlap, so shift-out and next-shift-in share cycles).

Compare to golden:

• The expected (golden) response is the good-machine result the ATPG/simulator computed.
• The tester compares the shifted-out bits to golden; a mismatch = a detected fault (a fail on that die).

Why shift dominates test time (link to 1.4):

• Each pattern costs ~N shift-in + N shift-out cycles but only ~1 capture cycle → shift ≈ all the time.
• Total ≈ chain length × patterns — the exact quantity compression (Ch7) attacks.

Chain integrity comes first:

• Before coverage means anything, a flush/chain-integrity test shifts a known pattern (e.g. 0011) through each chain and checks it arrives intact — proving the shift path works.

5. Mental Model — a bucket brigade with a snapshot

Picture a bucket brigade (the chain) that can also take a group photo (capture).

• Shift in: you pass buckets hand-to-hand from the entrance (scan-in) until every person holds the exact bucket you chose — that's loading the stimulus (controllability). It takes as many passes as there are people (N).
• Capture: everyone acts at once on what they're holding — the combinational logic fires, and each person now holds a new bucket (the response). This is one instant.
• Shift out: you pass buckets hand-to-hand to the exit (scan-out) to see what each person ended up with (observability) — and you feed the next round's buckets in the entrance at the same time (overlap).
• A judge (the tester) checks each emerging bucket against the expected one (golden); a wrong bucket means a fault.
• First, though, you test the brigade itself — pass a known 0011 down the line and confirm it comes out 0011 (chain integrity). A broken brigade makes every round meaningless.

Load hand-to-hand, snapshot once, read out hand-to-hand — and prove the line works before you trust any round.

6. Working Example — a 4-cell chain loads, captures, unloads

Run the cycle on a 4-cell chain and detect a fault:

# Scan test cycle on a 4-cell chain — REPRESENTATIVE, SIMPLIFIED, tool-neutral:
# Chain length N = 4 ; SE = scan-enable ; shift clock pulses count in []
  Phase 1 SHIFT IN  (SE=1): load stimulus 1011 -> after 4 shift clocks, cells = [1,0,1,1]   (controllability)
  Phase 2 CAPTURE   (SE=0): 1 functional clock -> combinational logic responds -> cells capture -> e.g. [0,1,1,0]
  Phase 3 SHIFT OUT (SE=1): 4 shift clocks -> scan-out emits 0,1,1,0  (response)  || next pattern shifts IN
  COMPARE: golden response = 0110 ; observed = 0110 -> PASS   (a die with a fault would emit e.g. 0100 -> FAIL)
# Cost per pattern ~ N shift-in + N shift-out (+1 capture) -> SHIFT dominates (1.4).

# Chain-integrity (flush) test FIRST — REPRESENTATIVE:
  Shift 0011 0011 ... through each chain with SE=1, capture DISABLED for logic
  -> expect the SAME sequence to emerge at scan-out after N cycles of latency
  PASS -> the shift path works -> coverage numbers are trustworthy
  FAIL -> a chain defect (broken cell / SE stuck / clock issue) -> FIX before believing any pattern

The waveform shows the three phases and the two clock regimes:

7. Industry Flow — the scan cycle in the test program

The chain cycle is what the ATE executes for every pattern, after a chain-integrity gate:

8. Debugging Session — every pattern fails on silicon

9. Common Mistakes

• Trusting coverage before chain integrity. A broken chain makes every pattern meaningless — flush-test first.
• Forgetting the shift/capture overlap. Shift-out and the next shift-in share cycles — don't double-count.
• Treating capture as many cycles. Capture is one (or few) functional clocks; shift is the long part.
• Ignoring chain length = test time. N flops → N shift cycles/pattern → shift × patterns dominates (1.4).
• Misreading a dead chain as a yield crash. Near-total, uniform fails = chain integrity, not scattered defects.

10. Industry Best Practices

• Gate with a chain-integrity (flush) test before any capture patterns — always.
• Report shift cycles × patterns as the test-time driver; plan compression (Ch7) accordingly.
• Exploit shift-out / next-shift-in overlap to avoid wasted cycles.
• Distinguish chain-integrity fails from logic fails in diagnosis (uniform vs scattered).
• Keep the shift path clean — synchronous, well-timed SE and clocks (3.4, Chapter 4).

11. Senior Engineer Thinking

• Beginner: "Silicon fails every pattern — the yield is destroyed."
• Senior: "Near-total, uniform fails smell like a dead chain, not scattered defects. Did the chain-integrity flush pass? If a known 0011 doesn't come out intact, the shift path is broken — one bad cell or a stuck SE — and every compare fails for that reason. I prove chain integrity first; only then do coverage numbers mean anything."

The senior gates on chain integrity and reads uniform failure as a shift-path problem, not a yield catastrophe.

12. Silicon Impact

The shift-in / capture / shift-out cycle is the literal mechanism by which scan's promise (3.1) becomes tester pass/fail: controllability is delivered by shift-in (load any state), observability by shift-out (read any state), and the capture in between is the single cycle where the combinational logic under test actually responds. Understanding this cycle explains two things that dominate real DFT. First, test cost: because each pattern spends ~2N shift cycles and only ~1 capture cycle, shift overwhelmingly dominates test time (1.4) — which is the entire economic motivation for compression (Chapter 7). Second, bring-up discipline: the whole edifice presupposes a working shift path, so chain integrity is a hard precondition — a single broken cell or stuck scan-enable corrupts every load and unload and produces a near-total, uniform failure that can be catastrophically misread as a yield disaster (the story). A senior engineer therefore always flush-tests chains first and reads uniform failure as a shift-path problem versus scattered failure as real defects (1.1). For the RTL/DV engineer, the connections are direct: your flop count sets chain length (and thus shift cost), your synchronous discipline keeps chains shiftable, and the scan pattern is the artifact that turns your logic's modeled faults (Chapter 2) into binnable, diagnosable silicon results — the foundation on which ATPG (Ch5), coverage (Ch6), and the DPPM commitment (1.5) all rest.

13. Engineering Checklist

• Ran and passed a chain-integrity (flush) test before trusting any coverage.
• Confirmed the three-phase cycle: shift-in (SE=1) → capture (SE=0, one clock) → shift-out (SE=1).
• Exploited shift-out / next-shift-in overlap; counted shift cycles = chain length.
• Compared scan-out to golden and localized any mismatch to a fault/defect.
• Distinguished uniform (chain-integrity) fails from scattered (logic) fails in diagnosis.

14. Try Yourself

1. Draw a 4-cell chain (scan-in → cells → scan-out) and mark the Q → next SI links.
2. Shift in 1011 (4 clocks, SE=1); write the cell contents after loading.
3. Capture (SE=0, one clock) with an assumed combinational response; write the new cell contents.
4. Shift out (4 clocks, SE=1) and list the scan-out bit stream; compare to a golden response.
5. Write a chain-integrity test: shift 0011 through and state the expected scan-out — explain why this must pass first.

The cycle is tool-neutral — pen and paper (or a free simulator) suffices. Real scan patterns come from ATPG (Chapter 5). No paid tool required.

15. Interview Perspective

• Weak: "You shift test data into the flip-flops and shift the results out."
• Good: "Shift in a pattern with scan-enable high, capture one functional clock, shift the response out, compare to expected."
• Senior: "A scan chain wires scan cells Q→SI from a scan-in to a scan-out pin. The test cycle is three phases: shift in (SE=1) for N clocks to load the stimulus (controllability), capture (SE=0) for one functional clock so the combinational logic between flops responds and is captured, then shift out (SE=1) for N clocks to unload the response — overlapping the next pattern's shift-in — and the tester compares scan-out to the golden response. Because shift is ~2N cycles versus ~1 capture, shift dominates test time, which is why compression exists. And critically, all of this assumes the chain shifts correctly — so I always run a chain-integrity (flush) test first; a broken chain makes every pattern fail and masquerades as a yield disaster."

16. Interview / Review Questions

17. Key Takeaways

• A scan chain wires scan cells Q → next SI into a shift register, from a scan-in pin (head) to a scan-out pin (tail).
• The fundamental test cycle is three phases: shift in (SE=1) — N clocks to load the stimulus (controllability); capture (SE=0) — one functional clock where the combinational logic between flops responds and is captured; shift out (SE=1) — N clocks to unload the response (overlapping the next shift-in).
• The tester compares the shifted-out response to the golden (good-machine) response — a mismatch is a detected fault (a fail).
• Shift dominates test time: ~2N shift cycles vs ~1 capture cycle per pattern → chain length × patterns (1.4) — the target of compression (Ch7).
• Chain integrity is a precondition for all scan test — a flush test must prove each chain shifts a known pattern intact before any coverage is trusted; a broken chain fails uniformly and masquerades as a yield disaster. Next: 3.4 — shift vs capture modes.

18. Quick Revision

Scan chains — the fundamental test cycle. Cells wired Q → next SI, from scan-in to scan-out = a shift register. Cycle: SHIFT IN (SE=1, N clocks → load stimulus = controllability) → CAPTURE (SE=0, ONE functional clock → combinational logic responds, captured) → SHIFT OUT (SE=1, N clocks → unload response, overlaps next shift-in) → COMPARE to golden (mismatch = detected fault). Shift dominates (~2N shift vs ~1 capture per pattern → chain length × patterns = test time, 1.4). CHAIN INTEGRITY first: flush a known 0011 through and confirm it emerges intact — a broken chain fails uniformly and looks like a yield disaster. Next: 3.4 — shift vs capture modes.