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DFT · Chapter 0 · DFT Foundations

Testability: Controllability & Observability

Two ideas underpin all of DFT. Controllability is whether you can set an internal node to a chosen value, both 0 and 1, from the pins. Observability is whether you can see that node's value at the pins. A fault is testable only when you have both: you must control the fault site to the value that excites the fault, and observe the effect by propagating it along a sensitized path to an output. Miss either and no pattern can reveal the fault. The trouble is geometry, because deep internal nodes sit far from the inputs, so they are hard to control, and far from the outputs, so they are hard to observe. That is exactly why scan exists, buying both at every flop. This lesson makes the two ideas concrete and teaches you to tell a controllability problem from an observability one.

Foundation13 min readDFTControllabilityObservabilityTestabilityScan

Chapter 0 · Section 0.4 · DFT Foundations

Project thread — the single D flip-flop, now buried inside logic, is the perfect example: its d is hard to control and its q hard to observe from the pins. 0.5 turns this into the mental model for the whole course; Chapter 3 (scan) is the fix.

1. Why Should I Learn This?

Controllability and observability are the two axes of testability — every DFT technique exists to buy them.

  • Testable = controllable AND observable. Miss either → untestable → escape.
  • Deep nodes are hard to control (far from inputs) and observe (far from outputs).
  • Scan (Chapter 3) exists to buy both at every flop.

Master these two ideas and you can reason about coverage instead of memorizing rules.

2. Real Silicon Story — the node with two different problems

A coverage report showed a cluster of undetected faults. The team's first instinct was "add more patterns" — which did nothing.

Splitting the cluster revealed two different problems. Some faults were uncontrollable: their fault site sat behind logic that couldn't be driven to the exciting value from the pins — no pattern could excite them. Others were unobservable: they could be excited, but their effect had no sensitized path to any output — no pattern could see them. More patterns couldn't help either group, because the issue wasn't pattern search — it was missing controllability for one and missing observability for the other. The fixes were different: add a control point for the first, an observe point (or scan) for the second.

Lesson: undetected faults are a controllability problem, an observability problem, or both — and each has a different fix. Diagnosing which is the whole skill.

3. Concept — the two axes, and excite-then-propagate

Controllability — can I set this node?

  • Can I drive the node to 0 and to 1 from the pins?
  • Hard when the node is deep (many gates from any input), behind reconvergent logic, or driven by uncontrollable sources (internal clocks, buried state).

Observability — can I see this node?

  • Can I make the node's value appear at a pin?
  • Hard when the node is deep (many gates from any output) or its effect is masked by other logic.

Testing a fault = excite + propagate (needs both):

  1. Excite (controllability): drive the fault site to the value that makes a defective die differ from a good one. For a stuck-at-0, drive the site to 1 (good die = 1, defect = 0 → they differ). For stuck-at-1, drive it to 0.
  2. Propagate (observability): sensitize a path from the fault site to an output, so the difference reaches a pin and the tester sees a mismatch (0.2).
  • Both required. Excite without propagate → the difference exists but is invisible. Propagate without excite → there's nothing to see.

Why scan exists (preview):

  • Scan (Chapter 3) makes every flop loadable (perfect controllability of its output) and readable (perfect observability of its input) — collapsing the "deep node" problem: a buried flop becomes one hop from a controllable/observable point.
A deep node N far from primary inputs (hard to control) and far from primary outputs (hard to observe); testing needs excite plus propagatedrivecontrol?propagate?observePrimary inputsthe pins you can driveDeep logic conemany gates → hard toCONTROL NNode N (fault site)excite: drive to oppositeof stuck valueDeep logic conemany gates → hard toOBSERVE NPrimary outputsthe pins you can readTestable = control N+ observe Nexcite + propagate; scanbuys both (Ch3)12
Figure 1 — controllability and observability of a deep node (representative). A node N sits DEEP: many gates from any primary input (PI) -> hard to CONTROL (drive N to a chosen 0/1), and many gates from any primary output (PO) -> hard to OBSERVE (see N at a pin). To test a stuck-at fault on N you must EXCITE it (control N to the opposite value) AND PROPAGATE the effect along a sensitized path to a PO. Deep logic makes BOTH hard -> low testability. Scan (Ch3) inserts controllable/observable points at flops, so N becomes one hop from control and observe.

4. Mental Model — a puppet on strings, watched by a camera

Testing an internal node is like checking a puppet buried deep on a stage.

  • Controllability = the strings. Can you pull the strings to make this specific puppet strike a chosen pose (drive the node to 0 and 1)? Deep puppets have long, tangled strings — hard to control precisely.
  • Observability = the camera. Can the camera at the edge of the stage actually see this puppet, or is it hidden behind others (no sensitized path)? Deep puppets are off-camera.
  • To catch a broken puppet (a defect), you must both pose it into the position that reveals the break and have a camera that can see it. Either alone fails.
  • Scan is like giving every puppet its own short string and its own camera — suddenly the deepest puppet is trivially posed and seen.

Pull the string (control) and point the camera (observe) — or the broken puppet goes unnoticed.

5. Working Example — the buried flip-flop's two problems

Take the project's flop, buried: its d is driven by deep logic, its q feeds deep logic before any pin.

Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
# The buried flop (representative):
   PIs → ...deep AND/OR cone... → d → [ DFF ] → q → ...deep cone... → POs
# CONTROLLABILITY of d: to test a stuck-at on d, drive d to a chosen value FROM THE PINS.
#   -> but d is many gates deep; a specific pin combination may not exist that forces d=1 (uncontrollable).
# OBSERVABILITY of q: to test a stuck-at on q, propagate q's value to a PIN.
#   -> but q feeds deep reconvergent logic that MASKS it; no sensitized path to a PO (unobservable).
# RESULT: even a working flop is nearly UNTESTABLE — not for lack of patterns, but for lack of C and O.

The excite-then-propagate recipe for a specific fault (q stuck-at-0):

Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
# Test q stuck-at-0 (representative):
#   EXCITE (controllability): set up so q SHOULD be 1  (good die: q=1; defective die: q=0 -> they differ)
#     -> requires controlling d=1 and clocking, i.e. controllability of the flop's input
#   PROPAGATE (observability): sensitize a path q → PO so the 1-vs-0 difference reaches a pin
#     -> requires observability of q
#   If BOTH succeed: tester sees expected=1, defective die=0 -> MISMATCH -> caught (0.2)
#   If control fails: can't make q=1 -> nothing to see.   If observe fails: q=1 but path masks it -> invisible.

Scan fixes both (Chapter 3): the flop becomes a scan flop, so the tester loads d directly (controllability) and reads q directly (observability) — the deep cones no longer matter.

A representative testability report puts numbers on it:

Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
# Testability / controllability-observability report — REPRESENTATIVE (SCOAP-style: higher = harder):
  node       CC0    CC1    CO      note
  d          8      42     30      d hard to set to 1 (CC1 high) -> CONTROLLABILITY problem
  q          -      -      55      q hard to observe (CO high) -> OBSERVABILITY problem
# CC0/CC1 = effort to control to 0/1; CO = effort to observe. High numbers -> low testability.
# After SCAN: d and q become directly loadable/readable -> CC/CO collapse toward trivial.

6. Industry Flow — where C and O are bought

Controllability and observability are bought at specific stages — mostly by scan, at insertion time:

Controllability/observability across the flow: RTL baseline, synthesis preserves, scan buys C and O, ATPG excites and propagates, coverage reportsWhere C & O are boughtWhere C & O are bought1RTLsets baseline C/O — deep logic/uncontrolled clocks = low2Scan InsertionBUYS C (load flops) + O (read flops) — Ch3-43ATPGEXCITE (control) + PROPAGATE (observe) → patterns4Coveragefaults with both C and O get detected (Ch6)
Figure 2 — where controllability and observability come from (representative). RTL structure sets the BASELINE C/O (deep logic = low). SYNTHESIS preserves it. SCAN INSERTION (Ch3-4) BUYS C and O by making every flop loadable (controllability) and readable (observability). ATPG then EXCITES faults (using controllability) and PROPAGATES them (using observability) to build patterns, and reports COVERAGE (Ch6). Low C/O in RTL -> scan helps but can't fully fix combinational-only blind spots -> add test/observe points. Fix testability where it's cheapest: RTL.

7. Debugging Session — undetected faults: controllability or observability?

1

A cluster of undetected faults doesn't improve with more patterns, because the problem isn't pattern search — some faults are uncontrollable (can't be excited) and others unobservable (can't be propagated); diagnosing which, and applying the matching fix (control point vs observe point/scan), closes the gap

UNDETECTED = A CONTROLLABILITY OR OBSERVABILITY PROBLEM — DIFFERENT FIXES
Symptom

A coverage report shows a cluster of undetected faults. Adding more ATPG patterns (more effort, more search) doesn't help.

Root Cause

Missing controllability or observability — not a pattern-search problem. A fault is testable only with both: you must excite it (control the fault site to the value that makes a defect differ from good) and propagate the effect (observe it at a pin). More patterns only help when the fault is reachable — but here some faults are uncontrollable (no pin combination drives the fault site to the exciting value — often deep logic, an uncontrolled clock/reset, or buried state) and others are unobservable (the excited difference has no sensitized path to any output — deep reconvergent logic masks it). For the first group there is nothing to see; for the second, nothing can reach a pin. No amount of pattern search overcomes a structural lack of C or O — the fix must add the missing axis, and which axis differs per fault (a testability report, SCOAP-style, tells you which: high CC1 → controllability, high CO → observability).

Fix

Diagnose which axis is missing, then apply the matching fix. For uncontrollable faults: add controllability — a test/control point, or make the offending clock/reset test-controllable (Chapter 4), or (best) scan the driving flop so its value can be loaded (Chapter 3). For unobservable faults: add observability — a test/observe point, or scan the capturing flop so the effect can be read (Chapter 3). Then re-run ATPG: the faults now excite and propagate, and coverage closes (Chapter 6). The lesson: a fault is testable only if you can control its site to excite it AND observe the effect to propagate it — so undetected faults are a controllability problem, an observability problem, or both, each with a different fix; more patterns can't overcome a structural lack of C or O, and scan exists precisely to buy both at every flop. Diagnosing which axis (from the testability report) is the core skill — and most gaps trace back to RTL structure, so the cheapest fix is often in RTL. (Scan is Chapter 3; clock/reset controllability and test points Chapter 4; ATPG Chapter 5; coverage Chapter 6.)

8. Common Mistakes

  • Throwing more patterns at undetected faults. If the fault lacks C or O, no pattern can reach it.
  • Not distinguishing controllability from observability. They have different fixes (control point vs observe point).
  • Confusing testability with functionality. A node can work perfectly and still be untestable (buried).
  • Forgetting you need both to excite and propagate. One without the other detects nothing.
  • Ignoring uncontrolled clocks/resets. They kill controllability of everything behind them (Chapter 4).

9. Industry Best Practices

  • Reason in two axes — controllability and observability — for every testability question.
  • Read the testability report (SCOAP-style) to see which axis is weak per node.
  • Apply the matching fix — control point / observe point / scan the right flop.
  • Buy C and O with scan at every flop (Chapter 3) — the default DFT lever.
  • Fix C/O in RTL where possible — it's the cheapest place (deep logic, clocks, buried state).

10. Senior Engineer Thinking

  • Beginner: "These faults are undetected — run ATPG longer."
  • Senior: "Undetected means can't excite or can't observe — which one? High CC1 → controllability; high CO → observability. More patterns won't fix a structural C/O gap. I add the missing axis — a control point, an observe point, or scan the right flop — and check whether the RTL caused it."

The senior diagnoses controllability vs observability and adds the missing axis, rather than searching harder.

11. Silicon Impact

Controllability and observability are the currency of test coverage — every undetected fault is a node the tester couldn't reach, and every un-reached fault is a potential escape (0.2/Chapter 1). Because the two axes have different fixes, misdiagnosing them wastes effort (searching for patterns that can't exist) and leaves the gap open — a coverage hole that ships defects. The RTL engineer holds the deepest lever: deep logic, uncontrolled clocks/resets, and buried state all destroy C or O at the source, capping coverage before scan or ATPG even run (0.3). Understanding C and O as the two axes — and that scan buys both — is what turns DFT from a bag of tool commands into reasoning: every technique in this curriculum (scan, test points, BIST, boundary scan) is, at heart, a way to buy controllability and observability where the geometry of the logic took them away.

12. Engineering Checklist

  • Reasoned about both controllability and observability for the node/fault.
  • Confirmed a fault needs to excite (control to opposite of stuck value) and propagate (observe at a pin).
  • Diagnosed undetected faults as controllability vs observability (via testability report).
  • Applied the matching fix (control point / observe point / scan the right flop).
  • Checked whether RTL structure (deep logic, uncontrolled clocks, buried state) caused the C/O gap.

13. Try Yourself

  1. Bury the DFF: drive d from a deep AND/OR cone and route q through more logic to a pin.
  2. Controllability: try to find a pin combination that forces d=1. If the cone makes it impossible, d is uncontrollable to 1.
  3. Observability: try to sensitize a path from q to a pin. If reconvergent logic masks it, q is unobservable.
  4. Fix: replace the flop with a scan flop (Chapter 3) — now the tester loads d and reads q directly, and both problems vanish. Note that the flop's function never changed; only its testability did.

Any free simulator plus a testability-analysis mindset works; the reasoning is tool-independent. No paid tool required.

14. Interview Perspective

  • Weak: "Testability means the design works."
  • Good: "Controllability is setting an internal node from the pins; observability is seeing it at the pins; you need both to test a fault."
  • Senior: "A fault is testable only if I can control its site to excite it (drive it to the opposite of the stuck value) and observe the effect by propagating it along a sensitized path to an output. Deep nodes are far from inputs (low controllability) and far from outputs (low observability), so undetected faults are a controllability problem, an observability problem, or both — with different fixes. More patterns can't overcome a structural C/O gap; scan buys both at every flop. Testability is orthogonal to functionality — a working node can be untestable."

15. Interview / Review Questions

16. Key Takeaways

  • Controllability = can I set an internal node to a chosen value (0 and 1) from the pins? Observability = can I see that node at the pins? These are the two axes of testability.
  • A fault is testable only with both: excite it (control the fault site to the value that makes a defect differ from good — for stuck-at-0, drive to 1) and propagate the effect (observe it along a sensitized path to an output). One without the other detects nothing.
  • Deep internal nodes are far from inputs (hard to control) and far from outputs (hard to observe) — the deeper the logic, the lower both — so a working node can be untestable (testability ≠ functionality).
  • Undetected faults are a controllability problem, an observability problem, or both — with different fixes; more patterns can't overcome a structural C/O gap (diagnose which axis via a SCOAP-style testability report).
  • Scan exists to buy both — it makes every flop loadable (controllability) and readable (observability), collapsing the deep-node problem; most C/O gaps trace to RTL structure, so the cheapest fix is often in RTL. Next: 0.5 — a mental model for thinking about testability.

17. Quick Revision

Testability = CONTROLLABILITY (set a node from the pins, both 0 and 1) + OBSERVABILITY (see it at the pins). Test a fault = EXCITE (control site to opposite of stuck value) + PROPAGATE (sensitize a path to an output) — need both. Deep nodes = low C (far from inputs) + low O (far from outputs) → untestable even if working (testability ≠ functionality). Undetected faults = a C problem or an O problem (different fixes); more patterns can't fix a structural gap. Scan buys both at every flop (Ch3). Next: 0.5 — a mental model for testability.