Transition & Delay Faults

Chapter 2 · Section 2.3 · Fault Models

Project thread — 2.2 tested the counter for stuck nodes; here we test whether its carry path switches fast enough — an at-speed, two-pattern transition test.

1. Why Should I Learn This?

Timing defects are a major escape source, and only at-speed transition/delay tests catch them — stuck-at can't.

• Transition faults: slow-to-rise / slow-to-fall — a node that switches correctly but too slowly.
• Detection needs an at-speed, two-pattern test: initialize → launch → capture one rated-clock period later.
• Path-delay extends this to a whole critical path's cumulative delay.
• At-speed test validates silicon timing — the defects STA can't know about (per-die resistive vias).

2. Real Silicon Story — passed DC, failed at speed

A part shipped with excellent stuck-at coverage and passed every wafer/final structural pattern. But a fraction of dies failed in the customer's system — and only when the system ran the block at full frequency.

Failure analysis found resistive vias on those dies: the affected nodes switched to the right value, just too slowly to make the capture edge at rated speed. The stuck-at test clocked slowly, so the nodes always arrived — the defect was invisible to it. The defect was a timing defect, and the fault list had no transition faults.

The fix was to add an at-speed transition test: a two-pattern test that launches a transition and captures one rated-clock period later, so a slow node captures the wrong value and fails on the tester — before it ships. Lesson: stuck-at proves nodes aren't stuck; only at-speed transition/delay test proves they're fast enough.

3. Factory Perspective — how each role reads a transition/delay fault

• What the test engineer sees: at-speed patterns (two-pattern, with on-chip clock control) and transition/path-delay coverage — plus the clocking complexity of launching and capturing at rated speed.
• What the yield engineer sees: speed-related fails and binning by frequency (speed sorting) — dies that work slow but not fast, hinting at process/timing marginality.
• What the RTL/DV engineer sees: that critical paths (the ones STA flagged) are the ones at-speed test must cover — and that timing-marginal RTL shows up as transition-coverage holes.
• What management cares about: at-speed test is often mandatory for the DPPM/quality contract in automotive/high-frequency markets — a must-have, and a real test-cost line (1.4).

4. Concept — transition faults, at-speed two-pattern tests, path-delay

Transition fault model:

• Two faults per node: slow-to-rise (STR) and slow-to-fall (STF) — the node eventually reaches the value but not within one clock period.
• Unlike stuck-at (never changes), a transition fault does change — just too late. So a static test can't see it; you must time it.

Detection = at-speed, two-pattern test:

1. Initialize (pattern 1): set the node to the starting value (e.g. 0 for an STR test).
2. Launch (pattern 2): cause the node to make the target transition (0→1 for STR).
3. Capture at speed: apply the capture clock one rated period after launch. A good node arrives in time (captures new value); a slow node misses and captures the old value → mismatch → detected.

• Two launch styles (named, kept light): launch-off-capture (LOC) — launch and capture both come from functional-clock pulses after scan load; launch-off-shift (LOS) — the launch is the last scan-shift edge. LOS is easier to fill but stresses shift timing; LOC is more functionally realistic.
• Requires on-chip clock control (OCC) / PLL to deliver two fast, precisely-spaced edges.

Path-delay vs transition:

• Transition (gate/local): a single node is slow — models local delay defects; large, tractable fault list.
• Path-delay: the cumulative delay along a specific path exceeds the period — targets critical paths STA identified; far fewer, selected paths (you can't enumerate all paths — exponential).

The STA connection (the deep idea):

• STA proves the design can meet timing given the model (libraries, corners) — but it cannot know a particular die has a resistive via.
• At-speed test validates the silicon actually meets that timing — it's the manufacturing check that the timing STA signed off survived fabrication on each die.

The two models differ in scope — one node vs a whole path:

5. Mental Model — a sprinter who finishes, but not in time

Stuck-at asks 'can the runner move at all?' Transition/delay asks 'can the runner finish before the whistle?'

• A slow-to-rise node is a sprinter who does cross the finish line — just after the whistle (the capture edge). At a slow, untimed jog (DC test) they always finish, so they look fine. Only a stopwatch at race pace (at-speed capture) reveals they're too slow.
• You need two commands: 'on your marks' (initialize) then 'go' (launch), and you check the clock at the finish line (capture one rated period later).
• Path-delay is timing a relay team down a specific lane — the whole lane's total time matters, not one runner.
• STA is the coach's prediction that the team should finish in time; at-speed test is the actual timed race for this specific team on this specific day — it catches the runner who pulled a hamstring (a resistive via) the coach couldn't foresee.

Finishing isn't enough — you must finish before the whistle, and only a timed race proves it.

6. Working Example — a slow carry path on the counter

Target a transition fault on the counter's carry logic (the path that must switch each count):

# At-speed transition test — REPRESENTATIVE, SIMPLIFIED, tool-neutral:
# Target: carry node C  SLOW-TO-RISE (must go 0->1 as the count rolls over)
#   INIT  (pattern 1) : set state so C = 0        (e.g. count = ...0)
#   LAUNCH(pattern 2) : advance count so C must rise 0->1
#   CAPTURE           : one RATED clock period after launch
#   GOOD  die : C reaches 1 in time -> capture 1 -> matches golden
#   SLOW  die : C still rising at capture -> capture 0 -> MISMATCH -> DETECTED
# A slow/DC stuck-at test would let C reach 1 (clock is slow) -> PASS -> the slow die would ESCAPE.

# Path-delay tie-in — REPRESENTATIVE:
# STA flagged the counter's longest carry chain as the critical path.
# Path-delay test targets THAT path's cumulative delay < period.
# -> at-speed test proves the SILICON meets the timing STA PROMISED (per die), catching a resistive via STA can't know.

7. Industry Flow — where at-speed test sits

Transition/delay test rides on STA timing and on-chip clock control, after stuck-at:

8. Debugging Session — dies pass DC, fail at frequency

9. Common Mistakes

• Assuming stuck-at covers timing. Stuck-at checks static values — it cannot see 'too slow.'
• Testing transitions at a slow clock. A slow capture lets a slow node arrive → it passes → escape. Must be at-speed.
• Trying to enumerate all path-delay faults. Paths are exponential — target STA's critical paths only.
• Forgetting clock control. At-speed needs precise two-edge launch/capture (OCC/PLL), not the shift clock.
• Confusing at-speed test with STA. STA times the design; at-speed test times the silicon, per die.

10. Industry Best Practices

• Add at-speed transition test wherever frequency matters or DPPM is tight (automotive) — on top of stuck-at.
• Use STA to select path-delay targets — you can't enumerate all paths; cover the critical ones.
• Provide robust on-chip clock control (OCC) for precise launch/capture edges.
• Choose LOC vs LOS deliberately — LOC is more functional; LOS fills easier but stresses shift timing.
• Report transition coverage separately from stuck-at — different defect class, different signoff.

11. Senior Engineer Thinking

• Beginner: "It passed all our patterns — must be a functional bug in the field."
• Senior: "Fails only at speed, only some dies — that's a timing defect, not a bug, and stuck-at can't see it (no transition faults in the list). I add at-speed two-pattern transition tests — launch, capture one rated period later — so slow nodes fail on the tester. STA promised the design times; at-speed test proves this die does."

The senior recognizes 'passes DC, fails at speed' instantly as a transition defect and reaches for at-speed test.

12. Silicon Impact

Transition and delay faults are where DFT meets timing signoff, and getting them wrong is a premium-market killer. A part can hit 100% stuck-at coverage and still ship speed defects — nodes that switch too slowly — straight into the field, because stuck-at structurally cannot model 'too slow' (2.1: coverage is vs the model). At-speed transition test closes that gap by timing each node's transition with a two-pattern, rated-period-capture test; path-delay test extends it to the critical paths STA flagged. The unifying insight is that at-speed test is the manufacturing validation of the timing STA only predicted: STA reasons about the design under model corners, but cannot know that this die grew a resistive via — at-speed test catches that per die. The cost is genuine — at-speed clocking (OCC), more patterns, tighter DFT — and it directly raises test cost (1.4), which is why the decision is market-driven: automotive and high-frequency parts treat at-speed test as mandatory to hit their DPPM (1.5), while some low-frequency consumer parts lean mostly on stuck-at. For the RTL/DV engineer, the connection is direct: your critical paths are what at-speed test stresses, and timing-marginal RTL surfaces as transition-coverage holes and speed fails — so timing-aware design and DFT-friendly clocking pay off as cleaner at-speed signoff and fewer speed escapes.

13. Engineering Checklist

• Added at-speed transition test where frequency/DPPM demands it (automotive) — on top of stuck-at.
• Built path-delay faults from STA critical paths (not all paths).
• Provided on-chip clock control for precise launch/capture edges; chose LOC/LOS deliberately.
• Reported transition coverage separately from stuck-at.
• Confirmed the plan validates silicon timing per die, complementing STA.

14. Try Yourself

1. On the counter's carry node, define a slow-to-rise transition fault.
2. Write the two-pattern test: initialize carry=0, launch the rollover that drives carry 0→1, capture one rated period later.
3. Show the good die captures 1 (pass) and the slow die captures 0 (detected).
4. Explain why a slow (DC) clock would let the slow die pass — the escape.
5. Pick the counter's longest path (from STA intuition) and describe a path-delay target on it; state what STA promised vs what at-speed test proves.

The reasoning is tool-neutral; a free simulator can show good-vs-slow capture with two clock edges. Real at-speed patterns/OCC come from the DFT/ATPG flow (Chapters 5–6). No paid tool required.

15. Interview Perspective

• Weak: "A transition fault is a delay in the circuit."
• Good: "Transition faults are slow-to-rise/slow-to-fall — a node switches too slowly; you test them at speed."
• Senior: "The transition model targets slow-to-rise / slow-to-fall — a node that reaches the right value but not within a clock period — which stuck-at can't model because stuck-at only checks static values. Detection needs an at-speed two-pattern test: initialize, launch the transition, capture one rated period later (via LOC or LOS, with on-chip clock control) — a slow node captures the old value and mismatches. Path-delay extends this to a specific critical path's cumulative delay, targeting STA's paths. The big idea: at-speed test validates the silicon meets the timing STA only predicted — catching per-die defects like a resistive via STA can't know about. It's mandatory for automotive/high-frequency DPPM, at real test-cost."

16. Interview / Review Questions

17. Key Takeaways

• Stuck-at is blind to timing defects — a node that switches correctly but too slowly passes a DC test and escapes to the field at speed.
• The transition fault model captures this as slow-to-rise (STR) and slow-to-fall (STF) — a node that fails to complete its transition within one clock period.
• Detection needs an at-speed, two-pattern test: initialize → launch the transition → capture one rated clock period later (via LOC/LOS, with on-chip clock control); a slow node captures the old value and mismatches.
• Path-delay faults extend this to the cumulative delay along a specific critical path — targeted from STA's critical paths (all paths are exponential to enumerate).
• At-speed test validates that the silicon meets the timing STA only predicted — catching per-die defects (resistive vias) STA can't know — and is mandatory for automotive/high-frequency DPPM (1.5) at real test-cost (1.4). Next: 2.4 — bridging & IDDQ faults (shorts and leakage).

18. Quick Revision

Transition & delay — timing defects stuck-at can't see. Stuck-at = 'is it stuck?'; transition = 'is it fast enough?' TRANSITION fault = slow-to-rise (STR) / slow-to-fall (STF): switches correctly but not within a clock period. Detect with an AT-SPEED TWO-PATTERN test: initialize → launch → capture one RATED period later (LOC/LOS + on-chip clock control); slow node captures the OLD value → mismatch → detected. PATH-DELAY = cumulative delay along a specific critical path (target STA's paths). At-speed test validates SILICON timing STA only PREDICTED — catches per-die resistive vias. Mandatory for automotive/high-freq DPPM; real test-cost. Next: 2.4 — bridging & IDDQ faults.