Where DFT and GLS Intersect

Chapter 11 · Section 11.1 · Scan / DFT Interaction

Project thread — the mini-SoC ships with DFT/scan so it can be tested in production. This chapter is where GLS verifies that test logic; 11.5 root-causes a scan reset/X issue.

1. Why Should I Learn This?

The netlist you simulate has test logic in it — and test mode behaves differently from functional mode.

• DFT adds scan flops, chains, and scan-enable — a test-mode shift register.
• GLS verifies chain integrity, ATPG patterns, and test-mode reset/X.
• Functional GLS ≠ test-mode GLS; pattern GLS ≠ coverage (ATPG's job).

This opens the chapter (11.2 chains, 11.3 shift/capture, 11.4 ATPG, 11.5 scan reset/X).

2. Real Silicon Story — the test escape a pattern GLS would have caught

A chip's scan test behaved oddly on the tester — some patterns gave unexpected results, delaying bring-up while engineers debugged the tester setup.

The root cause was in the netlist: an X source in test mode (a non-scan flop feeding the chain) made certain patterns mismatch — and a pattern GLS run (simulating the ATPG patterns against the netlist) would have shown the mismatch before tape-out. Instead the DFT bug reached the tester. Adding pattern GLS to the flow caught the class going forward.

Lesson: GLS is where DFT bugs — chain breaks, test-mode X, pattern mismatches — are caught before silicon. Simulating the scan/ATPG in GLS is a distinct, valuable check.

3. Concept — the DFT⋂GLS intersection

What DFT adds to the netlist:

• Scan flops — a flop with a mux selecting functional D vs scan-in SI (11.2).
• Scan chains — scan flops wired SO → SI into shift registers.
• Scan-enable (SE) — selects shift (test) vs capture (functional) (11.3).
• Test control — test mode, test clock, ATPG patterns.

What GLS verifies at this intersection:

• Scan-chain integrity — data shifts cleanly end to end (11.2/11.3).
• ATPG pattern simulation — patterns simulate against the netlist without mismatch (11.4).
• Capture/functional interaction — shift then capture behaves (11.3).
• Test-mode reset & X — reset and X sources in test mode (11.5).

Two boundaries (accuracy):

• Functional GLS ≠ test-mode GLS — with SE asserted the design is a shift register, not its functional self; they are different runs.
• Pattern GLS ≠ fault coverage — pattern GLS confirms patterns simulate correctly (match ATPG's expected); fault coverage (what % of faults the patterns detect) is ATPG's metric, not GLS's.

Scope: GLS catches DFT simulation bugs before silicon; it stays dynamic, STA signs off timing (0.3).

4. Mental Model — the netlist has a second personality

The DFT netlist has two personalities, switched by the scan-enable.

• Functional personality (SE = 0, capture): the design does its real job — this is what functional GLS tests.
• Test personality (SE = 1, shift): the design becomes a single long shift register (the scan chain) you can load and read — this is what scan/pattern GLS tests.
• They share the same flops but behave completely differently — a bug in one may be invisible in the other.
• ATPG writes the test scripts (patterns) and grades how thorough they are (coverage); pattern GLS just rehearses the scripts against the netlist to check they play correctly (no mismatch) — it doesn't grade thoroughness.

Simulate both personalities; don't confuse rehearsing the script (pattern GLS) with grading it (coverage).

5. Working Example — functional vs test mode

The scan-enable switching personalities (representative):

// Scan flop in the netlist — REPRESENTATIVE. Mux selects functional D vs scan-in SI, per SE.
SDFFR u_ff (.D(func_d), .SI(scan_in), .SE(scan_en), .CK(clk), .RN(rst_n), .Q(q), .SO(q));
//  SE=0 (capture)  -> Q captures func_d   (FUNCTIONAL personality)
//  SE=1 (shift)    -> Q captures scan_in  (TEST personality: part of the shift register)

# Two GLS runs, two personalities (tool-neutral):
#   FUNCTIONAL GLS: SE=0 -> design does its real job (Ch1-10)
#   TEST-MODE GLS:  SE=1 -> design is a scan shift register (chain integrity, 11.2/11.3)
#   PATTERN GLS:    simulate ATPG patterns -> confirm they SIMULATE correctly (no mismatch, 11.4)
#   NOTE: pattern GLS != fault COVERAGE (that's ATPG). GLS checks simulation, not coverage %.

Practical context (representative, tool-neutral):

gls/
  netlist/soc.vg        # netlist WITH scan (scan flops, chains, SE)
  patterns/atpg.stil    # ATPG patterns (test vectors) + expected responses
  sdf/soc.sdf           # timing (at-speed patterns need it, Ch4)
  tb/tb_scan.v          # drives SE, scan-in/out, test clock; applies patterns
# FUNCTIONAL GLS: SE=0  |  TEST-MODE GLS: SE=1 (shift)  |  PATTERN GLS: apply atpg.stil, check no mismatch
# Boundary: GLS verifies simulation; ATPG measures fault COVERAGE.

Functional vs test-mode behaviour via scan-enable, as a real waveform:

6. Debugging Session — a test-mode behaviour read as a functional bug

7. Common Mistakes

• Debugging test-mode (SE = 1) behaviour as a functional bug. They're different runs.
• Expecting pattern GLS to report fault coverage. That's ATPG's metric.
• Treating a pattern mismatch as 'low coverage'. It's a simulation problem (11.4).
• Skipping test-mode/pattern GLS. DFT bugs then reach the tester.
• Forgetting the netlist has test logic. Scan flops behave differently with SE.

8. Industry Best Practices

• Run functional GLS and test-mode/pattern GLS — different personalities.
• Verify scan-chain integrity and ATPG pattern simulation in GLS before silicon.
• Root-cause a pattern mismatch as a simulation issue (11.4), not coverage.
• Get fault coverage from ATPG, not GLS.
• Verify test-mode reset and X sources (11.5).

Senior Engineer Thinking

• Beginner: "The design misbehaves with SE on — there's a functional bug."
• Senior: "SE = 1 is test mode — it's a shift register now, behaving correctly. That's a different run from functional GLS. And a pattern mismatch is a simulation issue, not a coverage number — ATPG measures coverage."

The senior separates functional from test-mode runs and pattern-simulation from coverage.

Silicon Impact

DFT is what makes a chip testable in production — and GLS is where its test logic is verified before silicon. A DFT bug that escapes to the tester — a broken scan chain, a test-mode X source, a pattern mismatch — causes test escapes (bad chips passing) or yield loss (good chips failing), and delays bring-up while engineers debug the tester instead of the design (0.3). Pattern GLS (simulating ATPG patterns against the netlist) catches these before tape-out. The two boundaries keep the methodology honest: test-mode ≠ functional (simulate both), and pattern GLS ≠ coverage (GLS verifies simulation; ATPG measures coverage). Getting DFT⋂GLS right is what makes the manufacturing test actually work.

Engineering Checklist

• Ran functional GLS (SE = 0) and test-mode/pattern GLS (SE = 1) — different runs.
• Verified scan-chain integrity and ATPG pattern simulation (no mismatch).
• Treated a pattern mismatch as a simulation issue (11.4), not coverage.
• Got fault coverage from ATPG, not GLS.
• Checked test-mode reset and X sources (11.5).

Try Yourself

1. Take a netlist with scan flops; run functional GLS (SE = 0) — the design does its real job.
2. Observe: assert SE = 1 — the flops now shift (scan personality), ignoring functional inputs.
3. Change: apply a scan shift pattern and read the scan-out chain.
4. Expect: the data shifts through — a test-mode run, distinct from functional. Note the design 'misbehaves' functionally under SE because it's correctly in test mode.

Any free Verilog simulator with scan-flop cells reproduces functional vs test-mode behaviour. No paid tool required for the concept.

Interview Perspective

• Weak: "GLS just simulates the netlist."
• Good: "The netlist has scan logic; GLS verifies scan chains shift and ATPG patterns simulate before silicon."
• Senior: "DFT adds scan flops, chains, and a scan-enable, so the netlist has a functional and a test personality — different GLS runs. GLS verifies chain integrity, pattern simulation, and test-mode reset/X, catching DFT bugs before the tester. Crucially, pattern GLS confirms patterns simulate correctly — it doesn't measure fault coverage, which is ATPG's job."

9. Interview / Review Questions

10. Key Takeaways

• DFT adds scan logic to the netlist — scan flops (mux-D, 11.2), scan chains (SO→SI), a scan-enable (SE), and test control — turning the design into a shift register in test mode.
• GLS verifies the DFT⋂GLS intersection before silicon: scan-chain integrity, ATPG pattern simulation (no mismatch, 11.4), capture/functional interaction (11.3), and test-mode reset/X (11.5).
• Functional GLS (SE = 0) and test-mode GLS (SE = 1) are different runs — the design has a functional and a test personality; don't debug one as the other.
• Pattern GLS confirms patterns simulate correctly (no mismatch); it does not measure fault coverage — that's ATPG's metric.
• GLS catches DFT simulation bugs (chain breaks, test-mode X, mismatches) before the tester; it stays dynamic, STA signs off timing (0.3). Next: 11.2 — scan chains in the netlist.

Quick Revision

DFT adds scan (scan flops mux-D, chains SO→SI, SE, test control) → test-mode shift register. GLS verifies chain integrity, ATPG pattern simulation (no mismatch), capture interaction, test-mode reset/X — before silicon. Functional GLS (SE=0) ≠ test-mode GLS (SE=1) (different runs). Pattern GLS = simulate correctly, NOT fault coverage (ATPG's metric). Next: 11.2 — scan chains in the netlist.