Working Example: A Power-Gated Clock-Gated Block

Chapter 10 · Section 10.6 · Low-Power GLS

Project thread — the mini-SoC's peripheral block gains power gating on top of the clock gating from 8.6. A correctly-sequenced power-gated block is the foundation of the SoC's power management. Chapter 11 takes scan/DFT — where test logic meets all this.

1. Why Should I Learn This?

Real blocks combine clock gating and power gating — and the interactions are where bugs hide.

• Correct shutdown: gate clock → isolate → save → power off.
• Correct wake: power on → restore → de-isolate → un-gate clock.
• The failures are the whole chapter: corruption leak, lost state, bad sequence.

It integrates 10.1–10.5 on one block and closes the chapter.

2. Real Silicon Story — the power-gated block that corrupted the bus

A peripheral block was power-gated to save energy. When it powered down, the always-on bus it fed briefly went X, occasionally hanging the SoC.

The block's output had no isolation (10.3): on power-down its logic corrupted to X (10.2, expected), and that corruption leaked onto the bus because nothing clamped it. (The clock gating was fine — the clock was stopped first.) Adding isolation on the block's output — asserted before power-down — clamped it to the bus's inactive level, and the leak stopped.

Lesson: a power-gated block's outputs feeding an ON domain must be isolated — its power-down corruption leaks otherwise. Clock gating alone doesn't contain it; isolation does.

3. Concept — the power-gated clock-gated block

The block (two power-saving mechanisms):

• Clock gating (8.6) — an ICG stops the block's clock when idle (dynamic power).
• Power gating (10.1) — a power switch turns the block's domain off when unneeded (leakage).

Correct shutdown order (applying 10.5):

1. Gate the clock (8.6) — stop active edges before the transition.
2. Isolate outputs (10.3) — clamp so corruption can't leak.
3. Save retained state (10.4) — while still powered.
4. Power off — domain corrupts to X (10.2).

Correct wake order (reverse):

1. Power on — repower the domain.
2. Restore retained state (10.4).
3. De-isolate (10.3) — release clamps once valid.
4. Un-gate the clock (8.6) — resume clocking.

The failure modes (the whole chapter):

• No isolation → power-down corruption leaks to ON domains (10.3). (This example.)
• No retention → block wakes in lost state (10.4).
• Power off with clock running → corruption during active clocking (sequence, 10.5).
• Wrong sequence → leak / lost state / wrong value (10.5).

Scope (accuracy):

• Functional power-intent check (10.1) — corruption X models power-down (10.2). GLS dynamic; STA signs off timing (0.3).

4. Mental Model — mothballing a workshop

A power-gated clock-gated block is a workshop you mothball when not in use.

• Clock gating = turning off the machines when idle (they stop running, but the lights stay on).
• Power gating = shutting the whole workshop down — lights, power, everything (deep saving).
• Mothballing order: stop the machines (gate clock), seal the doors (isolate — nothing leaks out), lock the valuables in the safe (save retention), then cut the power (the dark workshop is "corrupt").
• Reopening: restore power, take the valuables out (restore), unseal the doors (de-isolate), restart the machines (un-gate clock).
• Skip sealing the doors (no isolation) and the dark, powered-off workshop leaks onto the street (corruption to the bus).

Seal before you cut power; unseal after you restore.

5. Working Example — the block, the leak, and the fix

The shutdown/wake sequence (representative):

// Power-gated clock-gated block control — REPRESENTATIVE (applies 10.5)
// SHUTDOWN:
clk_en   <= 0;   // 1. GATE CLOCK (8.6) -- stop active edges
iso_en   <= 1;   // 2. ISOLATE outputs (10.3) -- clamp before corruption
save_n   <= 0;   // 3. SAVE retention (10.4)
pwr_en   <= 0;   // 4. POWER OFF -> block corrupts to X (10.2)
// WAKE:
pwr_en   <= 1;   // 1. POWER ON
restore_n<= 0;   // 2. RESTORE (10.4)
iso_en   <= 0;   // 3. DE-ISOLATE (10.3)
clk_en   <= 1;   // 4. UN-GATE CLOCK (8.6)

// THE BUG (this example): block output feeds the ON bus WITHOUT isolation
assign bus_sig = blk_out;          // blk_out = X on power-down -> LEAKS onto the bus (10.3)
// THE FIX: isolate blk_out (clamp to bus-inactive level) when iso_en=1, before power-off

Practical context (representative, tool-neutral):

gls/
  netlist/blk.vg      # clock-gated + power-gated block
  upf/blk.upf         # power domain, switch, ISOLATION, RETENTION (10.1)
  lib/cells.v         # ICG + isolation + retention cell models
  tb/tb_blk.v         # power controller: clk_en, iso_en, save_n, pwr_en, restore_n
# SHUTDOWN: gate clock -> isolate -> save -> power off   |  WAKE: power on -> restore -> de-iso -> un-gate
# Verify: no corruption leaks to the bus; state survives; clock gated during transition.
# FUNCTIONAL power-intent check -- not power integrity (10.1).

The power-gated block: corruption leaking (no isolation) vs contained (with isolation), as a real waveform:

6. Debugging Session — corruption leaking onto the bus

7. Common Mistakes

• No isolation on power-gated outputs feeding ON domains — corruption leaks (10.3).
• Powering off with the clock running — corruption during active clocking (10.5).
• No retention on state the block must resume — wakes in lost state (10.4).
• Wrong shutdown/wake order — leak / lost / wrong value (10.5).
• Treating the corruption X as a logic bug — it's expected power-down modelling (10.2).

8. Industry Best Practices

• Shutdown: gate clock → isolate → save → power off.
• Wake: power on → restore → de-isolate → un-gate clock.
• Isolate every power-gated output feeding an ON domain (10.3).
• Retain state the block must resume (10.4); re-init the rest.
• Verify the full sequence in the power-aware log (no leak, state survives).

Senior Engineer Thinking

• Beginner: "The bus glitches when the block powers down — the bus logic is broken."
• Senior: "The block's power-down corruption is expected — is its output isolated before power-off? A power-gated output feeding the bus must be clamped. Let me check isolation and the shutdown sequence."

The senior recognises a power-gated-output leak, checks isolation and sequence, and reads corruption X as expected.

Silicon Impact

The power-gated clock-gated block is the archetype of low-power design — and this capstone shows the whole chapter's failure modes on one structure. A missing isolation on a power-gated output is a serious, system-level silicon bug: power-down corruption leaks onto an always-on bus, hanging or corrupting the SoC on every power event (0.3) — intermittent and power-sequence-triggered. Layer on the other failure modes — lost retention (block wakes wrong), bad sequencing (corruption during active clock, or a wake-order flash) — and the block becomes a minefield that only power-aware GLS running the full sequence can clear before tape-out. Getting it right — clock gating + power gating + isolation + retention + correct sequencing — is what makes aggressive power management safe, and it's the functional foundation the mini-SoC's power domains depend on.

Engineering Checklist

• Shutdown: gate clock → isolate → save → power off (10.5).
• Wake: power on → restore → de-isolate → un-gate clock (10.5).
• Isolation on every power-gated output feeding an ON domain (10.3).
• Retention on state the block must resume (10.4); re-init the rest.
• Verified no leak, state survives, clock gated during transition (power-aware log).

Try Yourself

1. Build a block that is clock-gated and power-gated; shut it down as gate clock → isolate → save → power off and feed its output to an ON bus.
2. Observe: with isolation, the bus stays clean; the block's corruption X is contained.
3. Change: remove the isolation on the output.
4. Expect: power-down corruption leaks onto the bus (X). Re-add isolation (before power-off); then try powering off with the clock still running and a de-isolate-before-restore wake to reproduce the other failure modes.

Power-aware simulation with ICG, isolation, and retention cells is an EDA-tool feature; behaviour is standardized and illustrated tool-neutrally here.

Interview Perspective

• Weak: "A power-gated block just turns off to save power."
• Good: "It clock-gates when idle and power-gates when off; shutdown gates the clock, isolates, saves, then powers off."
• Senior: "Shutdown order is gate clock → isolate → save → power off; wake reverses it. Its outputs feeding ON domains must be isolated, or the expected power-down corruption leaks onto the bus — the classic bug. Retention preserves resumable state. It's the whole chapter interacting, verified in power-aware GLS — a functional check, not power integrity."

9. Interview / Review Questions

10. Key Takeaways

• A power-gated clock-gated block saves power two ways: clock gating (ICG, stops the clock when idle, 8.6) and power gating (switches the domain off, 10.1).
• Correct shutdown: gate clock → isolate → save → power off (the domain then corrupts to X, 10.2); wake reverses: power on → restore → de-isolate → un-gate clock.
• Its outputs feeding ON domains must be isolated (10.3) — otherwise the expected power-down corruption leaks and hangs/corrupts the always-on domain (this example's bug).
• The chapter's failure modes all live here: missing isolation (leak), missing retention (lost state, 10.4), power off with clock running or wrong order (corruption/lost/wrong, 10.5).
• Read corruption X as expected power-down modelling (10.2); it's a functional power-intent check verified in power-aware GLS — not power integrity (10.1); GLS dynamic, STA signs off timing (0.3). This closes Chapter 10; next, Chapter 11 takes Scan / DFT Interaction.

Quick Revision

Power-gated clock-gated block: clock gating (ICG, 8.6) + power gating (10.1). Shutdown: gate clock → isolate → save → power off (corrupts to X, 10.2). Wake: power on → restore → de-isolate → un-gate clock. Outputs feeding ON domains MUST be isolated (10.3), or power-down corruption leaks (this bug). Failure modes: no iso (leak), no retention (lost state, 10.4), wrong order (10.5). Functional check, verified in power-aware GLS. Chapter 10 complete; next: Chapter 11 — Scan / DFT.