ATPG Pattern GLS & Mismatch Debug

Chapter 11 · Section 11.4 · Scan / DFT Interaction

Project thread — the mini-SoC's ATPG patterns are validated by pattern GLS. This lesson debugs a mismatch; 11.5 root-causes a scan reset/X issue that causes them.

1. Why Should I Learn This?

A pattern mismatch is a specific, common DFT-in-GLS failure — and debugging it is a first-divergence skill.

• A mismatch = simulated ≠ ATPG-expected — a simulation problem (not coverage).
• Usual causes: X source, at-speed timing, contention, protocol.
• Debug by finding the first failing flop and tracing the X/difference (Ch6/8).

This applies shift/capture (11.3) to real patterns and sets up the scan reset/X capstone (11.5).

2. Real Silicon Story — the mismatch that exposed an ATPG blind spot

Pattern GLS showed mismatches on several patterns. ATPG had marked those patterns clean — so the simulation was doubted.

The mismatch was real. A non-scan flop feeding the logic was uninitialized (X), and that X propagated into the captured response — but ATPG's model had treated that flop optimistically (assumed a value), so ATPG didn't see the X. The GLS run, with faithful X-propagation, exposed what ATPG's model missed (the same RTL-vs-gate X-optimism story as 6.4, now ATPG-vs-GLS). Fixing the X source (initializing the flop in test) cleared the mismatch.

Lesson: a pattern-GLS mismatch is a real simulation problem, and it often exposes something ATPG's model didn't (an X source, timing). Debug it — don't dismiss it because ATPG passed.

3. Concept — pattern GLS and mismatch debug

What pattern GLS does:

• ATPG generates patterns + expected responses.
• Pattern GLS simulates the patterns against the netlist (shift/capture, 11.3) and compares the simulated response to the expected.
• Match → the pattern simulates as ATPG predicted. Mismatch → simulated ≠ expected.

A mismatch is a simulation problem — common causes:

• X source — an uninitialized non-scan flop, a memory (uninit contents → X), or a black box (unmodelled → X) whose X propagates into the response (Ch6).
• At-speed timing — a delay-test pattern hits a timing violation → notifier X (Ch8).
• Bus contention — multiple drivers on a net → X.
• Protocol — SE/capture-timing issue (11.3).

Debug method (first divergence):

1. Find the first failing flop — the earliest point where simulated ≠ expected (later failures are often downstream propagation).
2. Trace the difference to its source — is it an X (from where? Ch6), a timing violation (Ch8), or contention?
3. Classify and fix the source (initialize the X source, fix at-speed timing, resolve contention, fix protocol).

Why ATPG and GLS can differ (accuracy):

• ATPG uses its own model — often zero-delay with specific X-handling (sometimes optimistic). So a GLS mismatch can expose what ATPG's model didn't (an X-optimism gap, an at-speed timing effect) — the ATPG-vs-GLS analog of 6.4.
• Pattern GLS ≠ fault coverage — it verifies simulation, not coverage (11.1). GLS stays dynamic; STA signs off timing (0.3).

4. Mental Model — a rehearsal that catches what the script assumed

Pattern GLS is a full-dress rehearsal of ATPG's script.

• ATPG wrote the script (patterns) and predicted how each scene plays (expected responses) — using its stage model (often zero-delay, assumed initial values).
• Pattern GLS performs the script on the real stage (the netlist, real timing, faithful X).
• A mismatch is a scene that plays differently than ATPG predicted — usually because the real stage has something the script's model assumed away: an unlit corner (X source), a slow set change (at-speed timing), or two actors on one mark (contention).
• To debug, find the first line that goes wrong (first failing flop) and trace back to the cause — don't re-watch every downstream scene it spoiled.

The rehearsal exposes the script's hidden assumptions; find the first wrong line and trace it.

5. Working Example — a mismatch and its first-divergence debug

The ATPG pattern and a mismatch (representative):

# ATPG pattern + expected (STIL-like) — REPRESENTATIVE
pattern 42:
  shift_in  : 1011_0010_...        # loaded scan state
  expected  : 0110_1001_...        # ATPG-predicted captured response
# Pattern GLS simulates -> compares captured response to 'expected'.

# Mismatch debug (first divergence, tool-neutral):
#   simulated : 0110_X001_...       # differs from expected at bit 4 (X)
#   expected  : 0110_1001_...
#   1) FIRST failing flop = bit 4 (an X)  -> later bits may be downstream propagation
#   2) trace bit 4's X to its source (Ch6): a non-scan flop? memory? black box? contention?
#   3) or at-speed TIMING (Ch8): did this pattern hit a timing violation -> notifier X?
#   4) classify + fix the SOURCE (init the X source / fix timing / resolve contention / protocol)
# NOTE: ATPG's model may be zero-delay/optimistic -> GLS exposed what it missed (6.4 analog).

Practical context (representative, tool-neutral):

# Pattern-GLS mismatch debug (tool-neutral):
#   1) run pattern GLS -> collect mismatching patterns/bits
#   2) for each: find the FIRST failing flop (first divergence) -- earliest sim != expected
#   3) trace it: X source (Ch6) | at-speed timing (Ch8) | contention | protocol (11.3)
#   4) fix the SOURCE; re-run -> mismatch clears
#   5) remember: GLS exposes what ATPG's (zero-delay/optimistic) model missed; coverage = ATPG

An expected-vs-actual mismatch from an X source, as a real waveform:

6. Debugging Session — a pattern mismatch from an X source

7. Common Mistakes

• Dismissing a mismatch because ATPG passed. ATPG's model differs (X/timing) — the mismatch is real.
• Debugging the last failing flop. Trace the first divergence; later failures are downstream.
• Not tracing the X to a source. An X from a non-scan flop/memory/black box is the usual cause (Ch6).
• Ignoring at-speed timing. Delay patterns can hit timing violations (Ch8).
• Treating a mismatch as a coverage number. It's a simulation problem (11.1).

8. Industry Best Practices

• Run pattern GLS to validate ATPG patterns simulate as predicted.
• Debug a mismatch by first divergence — first failing flop, then trace (Ch6/8).
• Classify the cause: X source / at-speed timing / contention / protocol.
• Initialize test X sources (non-scan flops, memories) and model black boxes.
• Get fault coverage from ATPG, not pattern GLS.

Senior Engineer Thinking

• Beginner: "ATPG passed these patterns, so the GLS mismatch is a sim glitch."
• Senior: "ATPG's model is zero-delay/optimistic — a GLS mismatch often exposes an X source it assumed away. Let me find the first failing flop and trace its X — non-scan flop? memory? at-speed timing? Then fix the source."

The senior treats a mismatch as a real problem, debugs first-divergence, and knows GLS exposes ATPG-model gaps.

Silicon Impact

Pattern GLS is the rehearsal that validates ATPG patterns before the tester — and a mismatch is a real issue that, unfixed, causes tester problems: patterns that don't behave as expected produce wrong pass/fail, causing test escapes or yield loss and derailing bring-up (0.3). Crucially, because ATPG's model differs from GLS (zero-delay, often X-optimistic), pattern GLS exposes classes ATPG missed — an uninitialized X source in test, an at-speed timing effect, a contention — exactly the X-optimism gap of 6.4, now in the test flow. Debugging by first divergence (find the first failing flop, trace the X/difference) turns a wall of mismatches into a single sourced fix. And the boundary holds: pattern GLS validates simulation; coverage is ATPG's — use each for its purpose.

Engineering Checklist

• Ran pattern GLS and collected mismatching patterns/bits.
• Debugged by first divergence (first failing flop), then traced (Ch6/8).
• Classified the cause (X source / at-speed timing / contention / protocol).
• Fixed the source (init X source, timing, contention, protocol); re-ran.
• Got fault coverage from ATPG, not pattern GLS.

Try Yourself

1. Run pattern GLS on a netlist with an uninitialized non-scan flop feeding the logic — some patterns mismatch.
2. Observe: find the first failing flop — it's an X.
3. Change: trace the X to the non-scan flop and initialize it in test (or make it a scan flop).
4. Expect: the mismatch clears. Then note ATPG had marked the pattern clean — GLS exposed the X source ATPG's model assumed away (6.4 analog).

Any free Verilog simulator can reproduce a pattern mismatch from an X source; ATPG pattern generation is an EDA-tool step. No paid tool required for the debug concept.

Interview Perspective

• Weak: "If ATPG generated the patterns, GLS should just pass."
• Good: "Pattern GLS simulates ATPG patterns and compares to expected; a mismatch is a real problem — usually an X source, timing, or contention."
• Senior: "ATPG uses a zero-delay, often optimistic model, so a GLS mismatch frequently exposes what it missed — an uninitialized X source, an at-speed timing violation, contention. I debug by first divergence: find the first failing flop, trace the X/difference to its source (Ch6/8), fix the source. Pattern GLS validates simulation; coverage is ATPG's."

9. Interview / Review Questions

10. Key Takeaways

• ATPG generates patterns + expected responses; pattern GLS simulates them against the netlist (11.3) and compares — a mismatch (simulated ≠ expected) is a real simulation problem.
• Usual causes: an X source (uninitialized non-scan flop, memory, black box → X propagating, Ch6), at-speed timing (violation → notifier X, Ch8), bus contention, or a protocol issue (SE/capture, 11.3).
• Debug by first divergence: find the first failing flop, then trace the X/difference to its source (Ch6/8) — later failures are usually downstream propagation.
• A GLS mismatch often exposes what ATPG's model didn't — ATPG is typically zero-delay/X-optimistic, so faithful GLS reveals an X source or timing effect it assumed away (the ATPG-vs-GLS analog of 6.4).
• Pattern GLS verifies simulation, not fault coverage (ATPG's metric, 11.1); GLS stays dynamic, STA signs off timing (0.3). Next: 11.5 — scan reset & X issues.

Quick Revision

Pattern GLS simulates ATPG patterns + expected and compares. Mismatch = simulated ≠ expected → real sim problem: X source (uninit non-scan flop / memory / black box, Ch6), at-speed timing (Ch8), contention, or protocol (11.3). Debug by first divergence (first failing flop → trace to source). A GLS mismatch often exposes what ATPG's zero-delay/optimistic model missed (6.4 analog). Pattern GLS ≠ coverage (ATPG's). Next: 11.5 — scan reset & X issues.