Scan Chains in the Netlist

Chapter 11 · Section 11.2 · Scan / DFT Interaction

Project thread — the mini-SoC's flops are scan flops wired into chains. This lesson reads the chain structure; 11.3 simulates shifting and capturing through it.

1. Why Should I Learn This?

You can't verify a scan chain you can't read — and a chain break is a classic, silicon-blocking DFT bug.

• Scan flops = flop + mux-D (functional vs scan-in), selected by SE.
• A chain wires Q/SO → SI from a scan-in port to a scan-out port.
• A break (mis-wired SI/SO, or a non-scan flop) stops the shift.

This grounds shift/capture (11.3) and ATPG patterns (11.4).

2. Real Silicon Story — the chain that shifted out garbage

A scan shift test produced wrong data at the scan-out — the loaded pattern didn't come back correctly.

Reading the netlist chain revealed a break: one flop in the path was an ordinary (non-scan) flop, not a scan flop — it had no SI path, so when the chain tried to shift through it, it captured functional data (or X) instead of the previous flop's SO. The chain was broken at that flop. Replacing it with a scan flop (restoring the SI → SO path) fixed the shift.

Lesson: a scan chain is only intact if every flop in the path is a scan flop with its SI wired to the previous SO. A non-scan flop or mis-wired SI/SO breaks the chain — shifted data comes out wrong.

3. Concept — scan flops and chains in the netlist

The scan flop:

• A flop with a mux on the data input: D (functional) vs SI (scan-in), selected by SE.
• SE = 0 → capture D; SE = 1 → capture SI (shift).
• Netlist cell: SDFFR (scan D-flop with reset) — pins D, SI, SE, CK, RN, Q (Q doubles as scan-out SO).

The scan chain:

• Scan flops wired SO → SI: scan_in → SI[0] … SO[0] → SI[1] … → SO[n] → scan_out.
• In shift mode (SE = 1), the whole chain is a shift register: one bit shifts per clock.
• Chain order = the order flops appear from scan-in to scan-out (follow SI → Q/SO → SI …).

Reading the chain in the netlist:

• Find the scan-in port, follow SI to the first scan flop's Q/SO, to the next flop's SI, … to the scan-out port.
• Every flop in the path must be a scan flop with SI correctly wired.

Chain breaks (integrity failures):

• Mis-wired SI/SO — a flop's SI not connected to the previous SO.
• Non-scan flop in the path — no SI path, so it captures functional data/X, not the shift.
• Result: data doesn't shift through correctly → wrong at scan-out (a chain-integrity failure GLS catches).

Scope: chain integrity is structural (does the shift register connect end to end?); GLS stays dynamic, STA signs off timing (0.3).

4. Mental Model — a bucket brigade passing water

A scan chain is a bucket brigade: each person (scan flop) passes the bucket (data bit) to the next on each clock.

• In shift mode, everyone passes down the line — a bucket poured in at the start (scan-in) travels bucket-by-bucket to the end (scan-out).
• Each person must be a brigade member (scan flop) who takes from the previous person (SI ← previous SO`).
• Drop a non-member in the line (a non-scan flop) — they don't take from the previous person (no SI), so they grab their own water (functional D/X) and the bucket never gets through.
• Mis-connect two people (SI/SO mis-wired) — the bucket goes to the wrong hands and the line breaks.

Every link must be a member, correctly connected, or the water (data) doesn't reach the end.

5. Working Example — reading a chain and a break

A scan chain in the netlist (representative):

// Scan chain in the netlist — REPRESENTATIVE. Follow SI -> Q/SO -> SI ...
SDFFR u_f0 (.D(d0), .SI(scan_in), .SE(se), .CK(clk), .RN(rst_n), .Q(q0));  // scan_in -> f0
SDFFR u_f1 (.D(d1), .SI(q0),      .SE(se), .CK(clk), .RN(rst_n), .Q(q1));  // f0.SO -> f1.SI
SDFFR u_f2 (.D(d2), .SI(q1),      .SE(se), .CK(clk), .RN(rst_n), .Q(q2));  // f1.SO -> f2.SI
assign scan_out = q2;                                                       // f2.SO -> scan_out
// Chain order: scan_in -> f0 -> f1 -> f2 -> scan_out. In shift (se=1) it's a 3-bit shift register.

// A BREAK — a non-scan flop dropped in the path (no SI) — REPRESENTATIVE
DFFR  u_bad (.D(d1), .CK(clk), .RN(rst_n), .Q(q1));   // ordinary flop: NO SI -> captures d1, not q0
// The chain is broken at u_bad: q1 = d1 (functional/X), not the shifted scan_in bit.

Practical context (representative, tool-neutral):

# Reading / checking a scan chain (tool-neutral):
#   1) find scan_in port -> follow SI to the first scan flop's Q/SO
#   2) follow Q/SO -> next flop's SI -> ... -> scan_out port (that's the chain ORDER)
#   3) every flop in the path must be a SCAN flop (SDFFx) with SI wired to the previous SO
#   4) a non-scan flop (DFFx, no SI) or mis-wired SI/SO = a BREAK -> shift fails
#   5) verify by shifting a known pattern in and reading it out (11.3)

Data shifting through an intact chain vs a break, as a real waveform:

6. Debugging Session — a scan chain that shifts out garbage

7. Common Mistakes

• A non-scan flop in the chain path. No SI → captures functional D/X → break.
• Mis-wired SI/SO. A flop's SI not on the previous SO → break.
• Not reading the chain order. You can't verify a chain you haven't traced.
• Assuming all flops are scan flops. Some may be excluded (clock/reset gen) — those break a chain if in the path.
• Not shifting a known pattern to test integrity.

8. Industry Best Practices

• Ensure every flop in a chain is a scan flop, SI on the previous SO.
• Read/trace the chain order (scan-in → … → scan-out).
• Verify integrity by shifting a known pattern (11.3).
• Watch for non-scan flops (clock/reset gen) accidentally in a path.
• Catch chain breaks in GLS before the tester.

Senior Engineer Thinking

• Beginner: "The scan-out is garbage — the test is broken."
• Senior: "Let me read the chain: SI → SO → SI …. Is there a non-scan flop or a mis-wired SI? A break means the bit never shifts through — I fix the scan path and re-shift a known pattern."

The senior reads the chain structure and verifies integrity by shifting a known pattern.

Silicon Impact

The scan chain is the backbone of manufacturing test — it's how the tester loads and reads internal state to detect fabrication defects. A chain break (non-scan flop, mis-wired SI/SO) is a silicon-blocking DFT bug: if the chain doesn't shift correctly, patterns can't be applied or read, so testability collapses — chips can't be properly tested, causing test escapes (defective chips shipping) or yield loss (good chips failing) (0.3). GLS catches a chain break before tape-out by reading the chain and shifting a known pattern through it. Because a broken chain can render an entire scan region untestable, chain integrity is a first-order DFT correctness concern — and reading the chain in the netlist is the foundational skill.

Engineering Checklist

• Every flop in each chain is a scan flop, SI on the previous SO.
• Traced the chain order (scan-in → … → scan-out).
• Verified integrity by shifting a known pattern (11.3).
• Checked for non-scan flops accidentally in a chain path.
• Caught any chain break in GLS before the tester.

Try Yourself

1. Build a 3-flop scan chain (SDFFR, SI ← previous Q), assert SE = 1`, and shift a known pattern in.
2. Observe: the pattern shifts through and appears at scan-out after 3 clocks (intact chain).
3. Change: replace the middle scan flop with an ordinary DFFR (no SI).
4. Expect: the scan-out is now wrong — the bit didn't shift through the break. Restore the scan flop and confirm the pattern returns intact.

Any free Verilog simulator with scan-flop cells reproduces chain shifting and breaks. No paid tool required.

Interview Perspective

• Weak: "A scan chain is just the flops connected together."
• Good: "Each scan flop has a mux selecting functional D or scan-in SI under SE; flops are wired SO → SI into a chain from scan-in to scan-out."
• Senior: "In shift mode the chain is a shift register of scan flops. I read it by following SI → Q/SO → SI from the scan-in port to the scan-out port. A break — a non-scan flop with no SI, or a mis-wired SI/SO — stops data shifting through, so I verify integrity by shifting a known pattern. Chain integrity is structural; GLS catches a break before the tester."

9. Interview / Review Questions

10. Key Takeaways

• A scan flop is a flop with a mux on its data input selecting functional D vs scan-in SI, controlled by SE — netlist cell e.g. SDFFR with D, SI, SE, CK, RN, Q/SO.
• A scan chain wires scan flops SO → SI into a shift register from a scan-in port to a scan-out port; chain order is the sequence SI → Q/SO → SI ….
• Read the chain by following SI → Q/SO → SI from scan-in to scan-out; every flop in the path must be a scan flop with SI on the previous SO.
• A break — a non-scan flop (no SI) or a mis-wired SI/SO — stops data shifting through, giving wrong scan-out (a chain-integrity failure).
• Chain integrity is structural — verify by reading the chain and shifting a known pattern (11.3); GLS catches a break before the tester (dynamic; STA signs off timing, 0.3). Next: 11.3 — simulating shift & capture.

Quick Revision

Scan flop = flop + mux-D (functional D vs scan-in SI, per SE); netlist SDFFR (D/SI/SE/CK/RN/Q(SO)). Scan chain = scan flops wired SO→SI, scan-in → scan-out (shift register in SE=1). Read it: follow SI→Q/SO→SI. Break = non-scan flop (no SI) or mis-wired SI/SO → shift fails → wrong scan-out. Verify by shifting a known pattern (11.3). Structural integrity; GLS catches it. Next: 11.3 — shift & capture.