SystemVerilog · Topic
SystemVerilog Operators — Width, Signedness & X Behaviour
Bitwise, logical, reduction, shift, arithmetic and equality operators — with the width, signedness and X rules that decide what each one actually computes.
Operators look like the least interesting part of the language and produce some of its most expensive bugs, because an operator expression is well-formed, type-correct and silently wrong. Three rules cause nearly all of it: a result does not widen to hold the mathematically correct answer, an expression is signed only if every operand is signed, and a comparison against an unknown value returns X rather than false. None of the three produces a warning, and each one has a failure mode where a check stops discriminating rather than failing.