GLS · Topic
Gate-Level Timing Violation Debug — Setup, Hold & Notifiers
Debugging setup, hold, width and recovery violations in gate-level simulation — timing checks, notifiers, and violations that are not real.
A timing-check violation in simulation means the model detected a condition its timing check was written to catch; it does not by itself mean the silicon will fail. Violations during reset, on paths that are false by design, or on clock-domain crossings that STA already waived are routine, and treating every one as a bug wastes days. The skill is triage: establish which violations correspond to paths that STA also signs off on, and investigate those first.