Real Violations vs Simulation Artifacts

Chapter 8 · Section 8.4 · Timing-Violation Debug

Project thread — the counter, FSM, and (in 8.6) a clock-gated block all produce firings that must be triaged. This lesson is the decision procedure 8.6 applies end to end.

1. Why Should I Learn This?

The two failure modes of violation debug are opposite and both dangerous.

• Waive a real one → a timing bug ships (0.3).
• Chase an artifact → wasted effort, or disabled checks masking real ones.
• The cure is a systematic triage, ending at STA.

This is the judgement that makes 8.2/8.3 actionable and prepares the clock-gate capstone (8.6).

2. Real Silicon Story — the checks disabled to "clean up" a log, and the bug that shipped

A timing log was full of violations. To "clean it up," the team disabled timing checks broadly — and the log went green.

Most firings had been artifacts (edge-aligned stimulus, reset-active checks). But buried among them was a real hold race. Disabling checks wholesale to silence the artifacts also silenced the real one, which then shipped and failed at the fast corner in silicon.

Lesson: don't silence artifacts by disabling checks wholesale — you mask real violations. Triage each firing; fix or waive by evidence (STA), not by turning checks off.

3. Concept — the triage: artifact vs real

Common artifacts (fix the setup, not the design):

• Edge-aligned stimulus — TB drove the input at the edge (5.3). Fix: drive clear of the window.
• Checks active during reset — fired before the design is defined (Ch7). Fix: gate checks during reset.
• Async domain crossing — check across an async boundary isn't meaningful (→ Ch9). Fix: handle as CDC.
• Wrong / mis-scaled corner — setup at fast corner, hold at slow corner, or bad SDF (3.4/4.4). Fix: right corner/SDF.
• Data glitch — a transient that settled (3.5). Fix: judge the settled value.

Real violations (fix the design):

• Long setup path (8.2), hold race / clock skew (8.3) — genuine path timing, confirmed by STA.

The triage procedure:

1. Reproduce — is it deterministic?
2. Read the message (8.1) — setup/hold, instance/pin, edge, margin.
3. Isolate — fix the suspected artifact cause (stimulus, reset-gating, corner) and see if it vanishes.
4. Correlate with STA — does STA (right corner) show a real violation on this path?
   • Vanishes on setup-fix / no STA violation → artifact.
   • Persists / STA confirms → real (design fix).

The rule:

• Don't waive a real violation; don't chase an artifact. STA is the arbiter of real timing (2.5/0.3).

4. Mental Model — a smoke alarm: fire or burnt toast?

A timing-check firing is a smoke alarm — it means something, but not necessarily a fire.

• Burnt toast (artifact): you opened the oven at the wrong moment (edge-aligned stimulus), the alarm is in the garage during construction (reset-active check), or it's a different building (async domain). Fix the situation, not the house.
• Real fire (real violation): there's genuine heat on the path — confirmed by the fire department (STA).
• Never rip out the alarm to stop the noise (disabling checks) — you'll miss the real fire.

Investigate the cause of each alarm; call the fire department (STA) to confirm a real fire.

5. Working Example — triaging three firings

Three firings, three verdicts (representative):

# Triage log — REPRESENTATIVE (tool-neutral)
# Firing A: $hold at u_dut/d_reg -- input driven AT the edge by the TB
#   isolate: drive input a skew AFTER the edge (5.3) -> firing VANISHES -> ARTIFACT (fix stimulus)
#
# Firing B: $setup at u_ctrl/s_reg -- fires DURING reset assertion
#   isolate: gate timing checks while in reset (Ch7) -> VANISHES -> ARTIFACT (reset-active check)
#
# Firing C: $hold at u_cnt/q_reg[3] -- persists with clean stimulus, out of reset, fast corner
#   correlate: STA (fast corner) CONFIRMS a hold race on this path -> REAL -> design fix (8.3)

# The rule, applied:
#   A, B  -> artifacts: fix the RUN (stimulus, reset-gating). Do NOT touch the design.
#   C     -> real:      fix the DESIGN (add delay / skew). Do NOT waive it.
#   NEVER disable checks wholesale to silence A/B -- it would also hide C.

Practical context (representative, tool-neutral):

# Triage procedure (tool-neutral):
#   1) reproduce + read the message (8.1)
#   2) isolate: fix the suspected setup cause -> does it VANISH?
#        edge-aligned stimulus (5.3) | reset-active check (Ch7) | async crossing (Ch9)
#        wrong corner / mis-scaled SDF (3.4/4.4) | data glitch (3.5)
#   3) if it PERSISTS -> correlate with STA (right corner): confirmed = REAL
#   4) fix: artifact -> the RUN; real -> the DESIGN. Never disable checks wholesale.

An artifact firing that vanishes on isolation, as a real waveform:

6. Debugging Session — a log of firings, triaged (not disabled)

7. Common Mistakes

• Disabling checks wholesale to clean a log. Masks real violations among artifacts.
• Assuming all firings are noise (or all real). A log is a mix — triage each.
• Skipping the isolation test. Fixing the suspected cause and re-running is the fastest classifier.
• Not correlating with STA. STA is the arbiter of real timing (0.3).
• Fixing an artifact at the design (or a real one at the run). Match the fix to the verdict.

8. Industry Best Practices

• Triage every firing (reproduce → read → isolate → correlate with STA).
• Fix artifacts at the run (stimulus, reset-gating, corner, async, glitch).
• Fix real violations at the design (retime/pipeline, hold buffers/skew, 8.2/8.3).
• Never disable checks wholesale — gate specific, justified artifacts only.
• Let STA be the arbiter of real timing.

Senior Engineer Thinking

• Beginner: "The log is full of violations — let me disable the checks."
• Senior: "It's a mix. I isolate each: does it vanish when I fix stimulus/reset/corner? Then it's an artifact. Does it persist and STA confirms? Then it's real. I never bulk-disable — that hides the real one."

The senior triages each firing to a verdict and reserves STA as the arbiter, never bulk-disabling checks.

Silicon Impact

This triage is where timing bugs are caught or lost. The dangerous outcomes are symmetric: waiving a real violation (or masking it by disabling checks) ships a path-timing bug that fails at a corner in silicon (0.3); chasing artifacts wastes schedule and can erode trust in GLS. A disciplined triage — isolate, correlate with STA — keeps the signal high: artifacts are fixed cheaply at the run, real violations are fixed at the design, and no real violation is silenced to quiet the noise. Because the artifacts (edge-aligned stimulus, reset-active checks, async crossings, wrong corner, glitches) are common, this skill is what makes a gate-level timing log trustworthy rather than overwhelming.

Engineering Checklist

• Reproduced and read each firing (8.1).
• Isolated by fixing the suspected artifact cause — did it vanish?
• Correlated persistent firings with STA (right corner).
• Fixed artifacts at the run, real violations at the design.
• Never disabled checks wholesale — masks real violations.

Try Yourself

1. Produce three firings: one from edge-aligned stimulus (5.3), one from a check active during reset (Ch7), one from a real short-path hold race (8.3).
2. Observe: read each message (8.1).
3. Change: isolate — drive clear of the edge, gate checks during reset — and see the first two vanish.
4. Expect: the third persists and STA confirms it → real (design fix). Prove the triage: two artifacts (run fix), one real (design fix); never disable checks to hide them.

Any free Verilog simulator reproduces the artifact firings; STA correlation uses your timing tool of choice. No paid tool is required to learn the triage.

Interview Perspective

• Weak: "A timing violation means the design has a timing bug."
• Good: "Some firings are artifacts (edge-aligned stimulus, reset-active checks, wrong corner); real ones are confirmed by STA."
• Senior: "I triage each firing: read it, isolate the suspected cause, and correlate with STA. Vanishes on a run-fix → artifact; persists and STA confirms → real. I fix artifacts at the run and real violations at the design, and I never disable checks wholesale — that masks the real ones. STA is the arbiter."

9. Interview / Review Questions

10. Key Takeaways

• A timing-check firing is not automatically real, nor automatically noise — a log mixes artifacts and real violations.
• Artifacts (fix the run): edge-aligned stimulus (5.3), checks active during reset (Ch7), async-crossing checks (→ Ch9), wrong/mis-scaled corner (3.4/4.4), data glitches (3.5).
• Real violations (fix the design): long setup path (8.2), hold race / clock skew (8.3) — confirmed by STA.
• Triage systematically: reproduce → read (8.1) → isolate (does fixing the suspected cause make it vanish?) → correlate with STA.
• Don't waive a real violation; don't chase an artifact; never disable checks wholesale (it masks the real ones). STA is the arbiter of real timing (2.5/0.3). Next: 8.5 — timing checks, notifiers & X-injection.

Quick Revision

Triage each firing — a log mixes artifacts and real. Artifacts (fix the RUN): edge-aligned stimulus (5.3), reset-active checks (Ch7), async crossings (Ch9), wrong corner/SDF (3.4/4.4), glitches (3.5). Real (fix the DESIGN): setup/hold path, STA-confirmed (8.2/8.3). Procedure: read (8.1) → isolate (vanishes = artifact) → correlate with STA (persists+confirmed = real). Never disable checks wholesale. STA is the arbiter. Next: 8.5 — timing checks, notifiers & X-injection.