Root-Causing a Setup Violation

Chapter 8 · Section 8.2 · Timing-Violation Debug

Project thread — the counter's increment path and the FSM's next-state logic are the kind of combinational paths a setup violation lives on. This lesson traces one; 8.3 does the opposite (hold).

1. Why Should I Learn This?

Setup is the "is the logic fast enough?" question — and root-causing it is a directed walk.

• Setup = data too late → trace the data path back from the endpoint.
• Causes: long path, wrong (fast) corner, too-fast clock, or edge-aligned stimulus.
• Distinguish real (design/STA) from artifact (corner/stimulus) before fixing.

This is the setup half of violation debug (8.3 is hold, 8.4 is real-vs-artifact).

2. Real Silicon Story — the setup violation that only the slow corner showed

A setup violation appeared in an STA-signoff review but not in an early GLS run — so it was doubted.

The GLS run had used a fast-corner SDF (MIN delays). Setup is worst at the slow corner (MAX delays, 3.4/4.4) — at the fast corner the path arrived early, so GLS couldn't show it. STA at the slow corner did. The path was a real long combinational path; the fast-corner GLS had simply been the wrong lens.

Lesson: setup is a slow/max-delay concern. A setup problem hides at the fast corner and shows at the slow corner (and in STA). Trace the path and use the right corner.

3. Concept — what a setup violation is, and its causes

Definition:

• Setup = data must be stable before the clock edge; a violation is data still changing inside the setup window → arrived too late (3.2).

Root causes (trace to decide):

• Long combinational path (real): the data path is genuinely too slow for the period — a design issue (retime, pipeline, restructure).
• Wrong corner (artifact/lens): setup is worst at the slow/MAX corner — a fast-corner run hides it; a mis-scaled SDF can fake it (3.4/4.4).
• Clock too fast (real): period below the path's requirement.
• Edge-aligned stimulus (artifact): the testbench changed the input at the edge → self-inflicted setup miss (5.3).

Root-causing method:

• Start at the endpoint (the flop/D pin in the message, 8.1).
• Trace the data path back to the startpoint — where does the time go?
• Check the corner (should be slow/MAX for setup) and the stimulus (driven clear of the edge?).
• Decide real vs artifact (8.4), then fix accordingly.

Scope: setup is judged exhaustively by STA at the slow corner — the GLS firing is a stimulus-specific flag (2.5/0.3).

4. Mental Model — did the runner reach the line before the gun?

A setup path is a runner who must cross the finish line (the flop's D) before the starting gun (the clock edge).

• Too late (setup violation) → the runner was still running when the gun fired.
• Why? The track was too long (long combinational path), the gun fired early (clock too fast), you timed them on a cool day (fast corner — they run fast, hiding a slow-day problem), or you started them late (edge-aligned stimulus).
• The fix depends on why: shorten the track (retime), slow the gun (clock), time on a hot day (slow corner — the honest test), or start on time (stimulus).

Trace where the time went before deciding.

5. Working Example — tracing a setup path

The setup message and the data path it points to:

# Setup violation — REPRESENTATIVE (8.1)
"$setup at u_fsm/state_reg[1] (D): D changed 0.02ns before posedge CK (limit 0.05ns)"
# Endpoint = state_reg[1].D. Trace the DATA PATH back to its startpoint:

// The data path feeding the endpoint — REPRESENTATIVE. A long next-state path.
// startpoint (a flop) -> many combinational cells -> endpoint state_reg[1].D
assign next_state = f(state, inputs);   // deep logic cone -> late arrival at state_reg[1].D
// Check: is this the SLOW/MAX corner? is the clock period right? is stimulus clear of the edge?

# Corner + stimulus checklist for THIS setup firing (tool-neutral):
#   corner:   slow/MAX? (setup worst here, 3.4/4.4)  fast-corner run HIDES it; mis-scaled SDF FAKES it
#   clock:    is the period below what the path needs? (too-fast clock)
#   stimulus: driven a skew AFTER the edge? (edge-aligned = TB-induced, 5.3)
#   real?     STA at the slow corner confirms a genuine long-path setup issue

Practical context (representative, tool-neutral):

# Root-cause a setup violation (tool-neutral):
#   1) endpoint from the message (8.1): which flop/D pin
#   2) trace the DATA PATH back to the startpoint — where's the delay?
#   3) corner check: setup is worst at SLOW/MAX (3.4/4.4) — right corner?
#   4) stimulus check: input driven clear of the edge? (else TB-induced, 5.3)
#   5) real long path -> design fix (retime/pipeline), CONFIRM with STA (slow corner)

A setup violation from a late data path, as a real waveform:

6. Debugging Session — a setup violation: real long path or artifact?

7. Common Mistakes

• Not tracing the data path. The endpoint is only the start — walk back to the cause.
• Debugging setup at the fast corner. Setup is worst at the slow/MAX corner (3.4/4.4).
• Missing edge-aligned stimulus. A TB-induced setup miss looks real (5.3).
• Slowing the clock for every setup issue. Sometimes the path must be redesigned.
• Treating the GLS firing as the proof. STA at the slow corner is the signoff (0.3).

8. Industry Best Practices

• Trace the data path from endpoint to startpoint — locate the delay.
• Use the slow/MAX corner for setup (right lens, 3.4/4.4).
• Rule out stimulus (driven clear of the edge, 5.3) before blaming the design.
• Confirm real setup with STA (slow corner) — then fix the design (retime/pipeline).
• Don't waive a real setup violation; don't chase an artifact.

Senior Engineer Thinking

• Beginner: "Setup violation — slow the clock."
• Senior: "Where did the time go? Let me trace the data path from the endpoint. Is this the slow corner? Is the stimulus clean? If it's a real long path, STA confirms and I retime it — not just slow the clock."

The senior traces the path, uses the slow corner, and distinguishes real from artifact before choosing a design fix.

Silicon Impact

A real setup violation is a genuine path-too-slow problem — left unfixed, the design fails at the slow corner in silicon (hot, low-voltage, slow process), an intermittent, corner-dependent failure (0.3). Root-causing it correctly — tracing the path, using the slow corner, confirming with STA — is what turns a GLS firing into a targeted design fix (retime, pipeline). Equally, spotting an artifact (wrong corner, edge-aligned stimulus) prevents wasted ECOs and needless clock relaxation. The discipline — trace, corner, real-vs-artifact — keeps real setup bugs off the tape-out without churning on false ones.

Engineering Checklist

• Traced the data path from endpoint (message) to startpoint.
• Used the slow/MAX corner (setup's worst case, 3.4/4.4).
• Ruled out edge-aligned stimulus (TB-induced, 5.3).
• Confirmed a real setup path with STA (slow corner).
• Fixed the design for a real path (retime/pipeline) — not just the clock.

Try Yourself

1. Build a flop fed by a long combinational path so D arrives late; run at the slow corner — a $setup violation fires.
2. Observe: trace D back to the long logic cone.
3. Change: run the same design at the fast corner.
4. Expect: the setup violation disappears (early arrival) — proving setup is a slow-corner concern, and that the fast-corner run was the wrong lens. Confirm the real path with STA.

Any free Verilog simulator with SDF timing checks reproduces a setup violation; corner behaviour follows the SDF. No paid tool required.

Interview Perspective

• Weak: "A setup violation means slow the clock."
• Good: "Setup is data arriving too late; trace the data path back — it's usually a long combinational path, worst at the slow corner."
• Senior: "I trace the data path from the endpoint, use the slow/MAX corner (setup's worst case), and rule out edge-aligned stimulus. A real long path is a design fix — retime or pipeline — confirmed by STA at the slow corner. The GLS firing is a stimulus-specific flag; STA is the exhaustive signoff."

9. Interview / Review Questions

10. Key Takeaways

• A setup violation is data arriving too late — still changing inside the setup window before the clock edge (3.2).
• Root-cause by tracing the data path back from the endpoint (the flop/pin in the message, 8.1) to its startpoint — find where the time went.
• Causes: long combinational path (real, design fix), too-fast clock (real), wrong (fast) corner or mis-scaled SDF (artifact/lens), edge-aligned stimulus (TB-induced artifact, 5.3).
• Setup is worst at the slow / max-delay corner — use it (3.4/4.4); a fast-corner run hides real setup issues.
• A real setup path is a design fix (retime/pipeline), confirmed by STA at the slow corner; the GLS firing is a stimulus-specific flag, not the proof (2.5/0.3). Next: 8.3 — root-causing a hold violation.

Quick Revision

Setup violation = data too LATE (inside the setup window before the edge). Trace the data path back from the endpoint. Causes: long path / too-fast clock (real → design fix, retime/pipeline), wrong (fast) corner / mis-scaled SDF or edge-aligned stimulus (artifact). Setup is worst at the SLOW/MAX corner (3.4/4.4) — a fast-corner run hides it. Confirm real with STA (slow corner); the GLS firing is a flag. Next: 8.3 — hold violation.