RTL Design Patterns Labs.
Thirty advanced block-level design problems in SystemVerilog — control logic, buffering, arbitration, pipelining, clock-domain crossing, subsystem integration, and memory, power and reliability patterns. Each lab is a specification you design to, the way RTL is written on a real chip team.
Six modules — control logic to reliability patterns
Control Logic and Sequential Design Patterns
Priority encoding, timers, registered output control, transaction FSMs and multi-mode counters.
RTL-01 · RTL-02 · RTL-03 · RTL-04 · RTL-21
Buffers, Queues, and Data Movement
FIFOs, skid buffers, SerDes, ping-pong buffering and multi-port register files.
RTL-05 · RTL-06 · RTL-07 · RTL-08 · RTL-22
Arbitration and Resource Sharing
Round-robin and weighted arbitration, shared resources with ordered responses, and crossbars.
RTL-09 · RTL-10 · RTL-11 · RTL-12 · RTL-23
Pipelining and Performance-Oriented RTL
Elastic pipelines, pipelined arithmetic, hazard control and area/timing trade-offs.
RTL-13 · RTL-14 · RTL-15 · RTL-16 · RTL-24 · RTL-25
Robust RTL and Subsystem Integration
Clock-domain crossing, watchdogs, DMA-style control and reset sequencing.
RTL-17 · RTL-18 · RTL-19 · RTL-20 · RTL-26
Advanced Memory, Power, and Reliability Patterns
SRAM control, clock-enable power reduction, SECDED protection and transaction tracking.
RTL-27 · RTL-28 · RTL-29 · RTL-30
Lab numbers are stable IDs (Lab 21 is RTL-21); labs are listed in module order.
All 30 labs
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Module 1Control Logic and Sequential Design Patterns
Priority encoding, timers, registered output control, transaction FSMs and multi-mode counters.
- Lab 1Control Logic and Sequential Design Patterns
Parameterized Priority Encoder
Design a parameterized priority encoder with valid indication and deterministic priority.
Advanced·60 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 2Control Logic and Sequential Design Patterns
Programmable Timer Controller
Design a timer supporting start, pause, resume, restart, and terminal-count signaling.
Advanced·75 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 3Control Logic and Sequential Design Patterns
Registered Output Switching Controller
Design a glitch-free registered output controller with programmable switching delays.
Advanced·75 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 4Control Logic and Sequential Design Patterns
Transaction Control FSM
Design an FSM with backpressure, timeout recovery, and error handling.
Advanced·90 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 21Control Logic and Sequential Design Patterns
Programmable Multi-Mode Counter
Design a programmable counter supporting multiple counting modes, saturation, and overflow detection.
Advanced·75 min·Testbench·4 challengesAdvancedPublishedPaid
Module 2Buffers, Queues, and Data Movement
FIFOs, skid buffers, SerDes, ping-pong buffering and multi-port register files.
- Lab 5Buffers, Queues, and Data Movement
Parameterized Synchronous FIFO
Design a synchronous FIFO with simultaneous read/write support and full/empty detection.
Advanced·90 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 6Buffers, Queues, and Data Movement
Ready/Valid Skid Buffer
Design a skid buffer preventing data loss under ready/valid backpressure.
Advanced·75 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 7Buffers, Queues, and Data Movement
Configurable Serializer and Deserializer
Design a serializer/deserializer with framing and backpressure.
Advanced·90 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 8Buffers, Queues, and Data Movement
Ping-Pong Buffer Controller
Design a double-buffer controller for independent producer and consumer operation.
Advanced·90 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 22Buffers, Queues, and Data Movement
Multi-Port Register File
Design a parameterized register file with configurable read/write ports and collision semantics.
Advanced·90 min·Testbench·4 challengesAdvancedPublishedPaid
Module 3Arbitration and Resource Sharing
Round-robin and weighted arbitration, shared resources with ordered responses, and crossbars.
- Lab 9Arbitration and Resource Sharing
Round-Robin Arbiter
Design an N-requester round-robin arbiter with fair grant rotation.
Advanced·75 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 10Arbitration and Resource Sharing
Weighted Round-Robin Arbiter
Design a programmable weighted round-robin arbiter with service guarantees under defined traffic assumptions.
Advanced·90 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 11Arbitration and Resource Sharing
Multi-Client Register Bank Controller
Design arbitration and response routing for multiple clients accessing a shared register bank.
Advanced·90 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 12Arbitration and Resource Sharing
Shared Multiplier Controller
Design a shared multiplier with request queuing and ordered responses.
Advanced·90 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 23Arbitration and Resource Sharing
Parameterized Crossbar Switch
Design a crossbar with destination decoding and output-port arbitration.
Advanced·105 min·Testbench·4 challengesAdvancedPublishedPaid
Module 4Pipelining and Performance-Oriented RTL
Elastic pipelines, pipelined arithmetic, hazard control and area/timing trade-offs.
- Lab 13Pipelining and Performance-Oriented RTL
Elastic Ready/Valid Pipeline
Design a parameterized elastic pipeline with stall propagation.
Advanced·90 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 14Pipelining and Performance-Oriented RTL
Pipelined Arithmetic Unit
Design an arithmetic unit with configurable pipeline stages and valid tracking.
Advanced·90 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 15Pipelining and Performance-Oriented RTL
Hazard-Aware Pipeline Controller
Design forwarding, stall, and flush control for a pipelined datapath.
Advanced·105 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 16Pipelining and Performance-Oriented RTL
Configurable Barrel Shifter
Design a barrel shifter and compare RTL area/timing trade-offs.
Advanced·75 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 24Pipelining and Performance-Oriented RTL
Pipelined Leading-Zero Detector
Design a leading-zero detector with parameterized width and latency.
Advanced·75 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 25Pipelining and Performance-Oriented RTL
Configurable Pipelined Reduction Tree
Design a reduction tree and evaluate timing/area trade-offs.
Advanced·90 min·Testbench·4 challengesAdvancedPublishedPaid
Module 5Robust RTL and Subsystem Integration
Clock-domain crossing, watchdogs, DMA-style control and reset sequencing.
- Lab 17Robust RTL and Subsystem Integration
Asynchronous Pulse/Event Transfer
Design an asynchronous event transfer circuit with event-rate constraints.
Advanced·90 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 18Robust RTL and Subsystem Integration
Asynchronous FIFO
Design a FIFO using Gray-coded pointers and synchronized status generation.
Advanced·120 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 19Robust RTL and Subsystem Integration
Programmable Watchdog Subsystem
Design watchdog timeout detection and safe recovery behavior.
Advanced·90 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 20Robust RTL and Subsystem Integration
Multi-Channel DMA-Style Controller
Design descriptor handling, arbitration, and backpressure for a DMA-style controller.
Advanced·120 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 26Robust RTL and Subsystem Integration
Reset Synchronization and Sequencing Controller
Design reset synchronization and sequencing across multiple dependent blocks.
Advanced·90 min·Testbench·4 challengesAdvancedPublishedPaid
Module 6Advanced Memory, Power, and Reliability Patterns
SRAM control, clock-enable power reduction, SECDED protection and transaction tracking.
- Lab 27Advanced Memory, Power, and Reliability Patterns
Parameterized SRAM Controller
Design an SRAM controller with programmable read latency, byte-write enables, and request/response handshaking.
Advanced·105 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 28Advanced Memory, Power, and Reliability Patterns
Clock-Enable-Based Low-Activity Datapath
Design idle detection, clock-enable control, state retention, and wake-up behavior.
Advanced·90 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 29Advanced Memory, Power, and Reliability Patterns
SECDED-Protected Register Bank
Design a register bank with error injection, single-bit correction, and double-bit error detection.
Advanced·120 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 30Advanced Memory, Power, and Reliability Patterns
Outstanding Transaction Tracker
Design transaction-ID tracking, completion matching, and out-of-order response handling.
Advanced·105 min·Testbench·4 challengesAdvancedPublishedPaid