Verilog HDL Labs.
A premium, practical Verilog lab library — from basic gates to complete controllers and projects. Every lab pairs fully explained DUT code with a commented, self-checking testbench, expected outputs, waveform guidance, debugging help and progressive challenges. Build real design-and-verification skill, one focused lab at a time.
A progressive path — gates to FSMs to projects
Logic Foundations
Gates, modeling styles, and the adder/subtractor building blocks every datapath is made of.
Combinational Design
Adders, muxes, decoders, encoders, comparators, converters, shifters, and a full ALU.
Sequential Design
Latches, every flip-flop and conversion, pulse detectors, and the full shift-register family.
Counters & Timing
Ripple, synchronous, modulo-N, ring, Johnson, LFSR counters, and safe clock-enable generation.
Finite State Machines
Moore/Mealy detectors and real controllers — traffic, vending, arbiter, handshake, and more.
Memory & Reusable Blocks
Synchronous ROM/RAM, a full/empty-checked FIFO, and a configurable PWM generator.
Portfolio Projects
Two complete, resume-ready builds: a UART with loopback verification and a 4-floor elevator controller.
All 60 labs & projects
Search and filter the full curriculum. Titles, previews and metadata are free to browse — full lab content requires the labs package.
Module 1Logic Foundations
Gates, modeling styles, and the adder/subtractor building blocks every datapath is made of.
- Lab 1Logic Foundations
Basic Logic Gates
Model AND, OR, NOT, NAND, NOR, XOR and XNOR and prove each truth table on a self-checking testbench.
Beginner·70 min·Testbench·3 challengesBeginnerPublishedPaid - Lab 2Logic Foundations
Gates Using Only NAND and NOR
Build every basic gate from NAND-only and NOR-only forms — the universal-gate identities behind real standard cells.
Beginner·90 min·Testbench·3 challengesBeginnerPublishedPaid - Lab 3Logic Foundations
Boolean Function Using Structural, Dataflow and Behavioral Modeling
Implement one Boolean function three ways and compare structure, readability and synthesis of each style.
Beginner·40 min·Testbench·2 challengesBeginnerPublishedPaid - Lab 4Logic Foundations
Half Adder
Sum and carry from two bits — the first datapath primitive, verified exhaustively.
Beginner·25 min·Testbench·1 challengeBeginnerPublishedPaid - Lab 5Logic Foundations
Full Adder
Add three bits and cascade half-adders — the cell every ripple and carry-lookahead adder reuses.
Beginner·30 min·Testbench·2 challengesBeginnerPublishedPaid - Lab 6Logic Foundations
Half Subtractor
Difference and borrow from two bits — the subtraction counterpart to the half adder.
Beginner·25 min·Testbench·1 challengeBeginnerPublishedPaid - Lab 7Logic Foundations
Full Subtractor
Three-input subtraction with borrow-in, built from half subtractors and ready to cascade.
Beginner·30 min·Testbench·2 challengesBeginnerPublishedPaid - Lab 8Logic Foundations
Four-Bit Ripple-Carry Adder
Chain four full adders into a parameter-ready adder and measure the carry-propagation delay it costs.
Beginner·40 min·Testbench·2 challengesBeginnerPublishedPaid
Module 2Combinational Design
Adders, muxes, decoders, encoders, comparators, converters, shifters, and a full ALU.
- Lab 9Combinational Design
Carry-Lookahead Adder
Trade area for speed: generate/propagate logic that beats the ripple adder's carry delay.
Intermediate·55 min·Testbench·2 challengesIntermediatePublishedPaid - Lab 10Combinational Design
Configurable Adder-Subtractor
One datapath that adds or subtracts under a mode bit using two's-complement and XOR inversion.
Intermediate·45 min·Testbench·2 challengesIntermediatePublishedPaid - Lab 11Combinational Design
BCD Adder
Add packed decimal digits with the +6 correction that keeps results valid BCD.
Intermediate·50 min·Testbench·2 challengesIntermediatePublishedPaid - Lab 12Combinational Design
Multiplexer Family
2:1 through 16:1 muxes, scalable and parameterized — the selection primitive behind every datapath.
Beginner·40 min·Testbench·2 challengesBeginnerPublishedPaid - Lab 13Combinational Design
Demultiplexer
Route one input to one of many outputs — the mirror of the mux, with clean default handling.
Beginner·35 min·Testbench·1 challengeBeginnerPublishedPaid - Lab 14Combinational Design
Binary Decoder
n-to-2ⁿ decoding with enable — address decode, memory selects, and one-hot generation.
Beginner·35 min·Testbench·1 challengeBeginnerPublishedPaid - Lab 15Combinational Design
Binary Encoder
Compress a one-hot input to a binary code — and see why a plain encoder needs a valid signal.
Beginner·35 min·Testbench·1 challengeBeginnerPublishedPaid - Lab 16Combinational Design
Priority Encoder
Resolve simultaneous requests by priority — the arbitration primitive under interrupt controllers.
Intermediate·40 min·Testbench·2 challengesIntermediatePublishedPaid - Lab 17Combinational Design
Magnitude Comparator
Greater / equal / less across N bits, cascadable so wide comparisons stay fast.
Beginner·40 min·Testbench·2 challengesBeginnerPublishedPaid - Lab 18Combinational Design
Parity Generator and Checker
Even/odd parity generation and checking — the simplest error-detection code, end to end.
Beginner·35 min·Testbench·2 challengesBeginnerPublishedPaid - Lab 19Combinational Design
Binary-to-Gray and Gray-to-Binary Converter
Both conversions — the single-bit-change code that makes CDC and rotary encoders safe.
Intermediate·40 min·Testbench·2 challengesIntermediatePublishedPaid - Lab 20Combinational Design
BCD-to-Seven-Segment Decoder
Drive a 7-segment display from a BCD digit — the classic FPGA-board bring-up block.
Beginner·40 min·Testbench·1 challengeBeginnerPublishedPaid - Lab 21Combinational Design
Barrel Shifter
Shift or rotate by any amount in one combinational stage — the mux-tree behind fast ALUs.
Advanced·55 min·Testbench·3 challengesAdvancedPublishedPaid - Lab 22Combinational Design
Four-Bit Arithmetic Logic Unit
An op-code-driven ALU with add, subtract, logic and shift plus status flags — the datapath capstone.
Advanced·120 min·Testbench·3 challengesAdvancedPublishedPaid
Module 3Sequential Design
Latches, every flip-flop and conversion, pulse detectors, and the full shift-register family.
- Lab 23Sequential Design
SR Latch
The cross-coupled storage element — set, reset, and the forbidden state, seen on a waveform.
Beginner·35 min·Testbench·1 challengeBeginnerPublishedPaid - Lab 24Sequential Design
Gated D Latch
Level-sensitive storage with an enable — and why unintended versions show up as latch-inference warnings.
Beginner·35 min·Testbench·2 challengesBeginnerPublishedPaid - Lab 25Sequential Design
D Flip-Flop with Synchronous and Asynchronous Reset
The workhorse register, both reset styles side by side — and how each affects synthesis and timing.
Beginner·40 min·Testbench·2 challengesBeginnerPublishedPaid - Lab 26Sequential Design
JK Flip-Flop
Set, reset, hold and toggle in one element — including the toggle case SR could never do.
Beginner·35 min·Testbench·1 challengeBeginnerPublishedPaid - Lab 27Sequential Design
T Flip-Flop
The toggle flop that becomes the first bit of every counter you'll build next.
Beginner·30 min·Testbench·1 challengeBeginnerPublishedPaid - Lab 28Sequential Design
Flip-Flop Conversions
Convert between D, T, JK and SR using excitation tables — the classic that proves you understand state.
Intermediate·50 min·Testbench·2 challengesIntermediatePublishedPaid - Lab 29Sequential Design
Edge and One-Cycle Pulse Detector
Turn a level change into a clean single-cycle pulse — the register-and-compare trick used everywhere.
Intermediate·40 min·Testbench·2 challengesIntermediatePublishedPaid - Lab 30Sequential Design
SISO Shift Register
Serial-in serial-out — the simplest shift register and a first look at serial datapaths.
Beginner·30 min·Testbench·1 challengeBeginnerPublishedPaid - Lab 31Sequential Design
SIPO Shift Register
Serial-in parallel-out — deserialize a bit stream into a parallel word.
Beginner·30 min·Testbench·1 challengeBeginnerPublishedPaid - Lab 32Sequential Design
PISO Shift Register
Parallel-in serial-out — load a word and shift it out one bit at a time, as UART TX does.
Beginner·30 min·Testbench·1 challengeBeginnerPublishedPaid - Lab 33Sequential Design
PIPO Register
Parallel-in parallel-out — the plain N-bit register that stores a bus in one clock.
Beginner·25 min·Testbench·1 challengeBeginnerPublishedPaid - Lab 34Sequential Design
Bidirectional Shift Register
Shift left or right under a direction control — one step from the universal register.
Intermediate·40 min·Testbench·2 challengesIntermediatePublishedPaid - Lab 35Sequential Design
Universal Shift Register
Hold, load, shift-left and shift-right selected by a 2-bit mode — the reusable register IP.
Intermediate·50 min·Testbench·2 challengesIntermediatePublishedPaid - Lab 36Sequential Design
Eight-Word Register File
Dual-read, single-write storage with address decode — the register file at a CPU's core.
Advanced·60 min·Testbench·3 challengesAdvancedPublishedPaid
Module 4Counters & Timing
Ripple, synchronous, modulo-N, ring, Johnson, LFSR counters, and safe clock-enable generation.
- Lab 37Counters & Timing
Asynchronous Ripple Counter
Chain toggle flops and watch the ripple delay — plus why async counters glitch on decode.
Beginner·35 min·Testbench·2 challengesBeginnerPublishedPaid - Lab 38Counters & Timing
Synchronous Up Counter
All flops on one clock — the correct, glitch-free way to count, with enable and reset.
Beginner·35 min·Testbench·1 challengeBeginnerPublishedPaid - Lab 39Counters & Timing
Synchronous Down Counter
Count down to zero with terminal-count detection — the basis of timers and delays.
Beginner·35 min·Testbench·1 challengeBeginnerPublishedPaid - Lab 40Counters & Timing
Synchronous Up/Down Counter
One counter that counts either direction under control — with saturation and wrap options.
Intermediate·40 min·Testbench·2 challengesIntermediatePublishedPaid - Lab 41Counters & Timing
Parameterized Modulo-N Counter
A width- and modulus-parameterized counter that rolls over at any N — reusable across the whole SoC.
Intermediate·45 min·Testbench·2 challengesIntermediatePublishedPaid - Lab 42Counters & Timing
BCD/Decade Counter
Count 0–9 and carry — cascade several to build the digits of a clock or frequency counter.
Intermediate·40 min·Testbench·2 challengesIntermediatePublishedPaid - Lab 43Counters & Timing
Ring Counter
A circulating one-hot token — the simplest way to generate non-overlapping phase clocks.
Beginner·35 min·Testbench·2 challengesBeginnerPublishedPaid - Lab 44Counters & Timing
Johnson Counter
The twisted-ring counter that yields 2N states from N flops with glitch-free decoding.
Intermediate·40 min·Testbench·2 challengesIntermediatePublishedPaid - Lab 45Counters & Timing
Linear-Feedback Shift Register
XOR-tap feedback that produces long pseudo-random sequences — the core of BIST and scramblers.
Advanced·55 min·Testbench·3 challengesAdvancedPublishedPaid - Lab 46Counters & Timing
Programmable Timer and Safe Clock-Enable Generator
Divide a fast clock into a slow tick the RIGHT way — a clock-enable pulse, not a gated clock.
Advanced·55 min·Testbench·3 challengesAdvancedPublishedPaid
Module 5Finite State Machines
Moore/Mealy detectors and real controllers — traffic, vending, arbiter, handshake, and more.
- Lab 47Finite State Machines
Moore Overlapping Sequence Detector
Detect a bit pattern with outputs tied to state — the canonical Moore FSM, overlaps allowed.
Intermediate·50 min·Testbench·2 challengesIntermediatePublishedPaid - Lab 48Finite State Machines
Mealy Overlapping Sequence Detector
The same detection with outputs on transitions — fewer states, and the Moore/Mealy timing difference on a waveform.
Intermediate·50 min·Testbench·2 challengesIntermediatePublishedPaid - Lab 49Finite State Machines
Traffic-Light Controller
A timed multi-state controller with configurable durations — the classic real-world FSM.
Intermediate·55 min·Testbench·2 challengesIntermediatePublishedPaid - Lab 50Finite State Machines
Vending-Machine Controller
Accept coins, track a running total, dispense and return change — an FSM with a small datapath.
Advanced·65 min·Testbench·3 challengesAdvancedPublishedPaid - Lab 51Finite State Machines
Round-Robin Arbiter
Grant a shared resource fairly with a rotating priority pointer — the arbiter real interconnects use.
Advanced·60 min·Testbench·3 challengesAdvancedPublishedPaid - Lab 52Finite State Machines
Request-Acknowledge Handshake Controller
A robust req/ack handshake — the flow-control pattern behind valid/ready and CDC interfaces.
Intermediate·50 min·Testbench·2 challengesIntermediatePublishedPaid - Lab 53Finite State Machines
Washing-Machine Controller
Sequence soak, wash, rinse and spin with timers and a pause — a multi-phase applied FSM.
Intermediate·55 min·Testbench·2 challengesIntermediatePublishedPaid - Lab 54Finite State Machines
Parking Occupancy and Gate Controller
Count entries/exits, track occupancy and drive an entry gate with a full indicator — FSM plus counter.
Advanced·60 min·Testbench·3 challengesAdvancedPublishedPaid
Module 6Memory & Reusable Blocks
Synchronous ROM/RAM, a full/empty-checked FIFO, and a configurable PWM generator.
- Lab 55Memory & Reusable Blocks
Synchronous ROM
A registered-output read-only memory initialized from data — how look-up tables infer as ROM.
Intermediate·40 min·Testbench·2 challengesIntermediatePublishedPaid - Lab 56Memory & Reusable Blocks
Synchronous Single-Port RAM
One address, read or write per clock — the block-RAM coding style that infers on real FPGAs.
Intermediate·50 min·Testbench·2 challengesIntermediatePublishedPaid - Lab 57Memory & Reusable Blocks
Synchronous FIFO with Full and Empty Checking
A single-clock FIFO with correct full/empty flags and pointer logic — the buffer every design needs.
Advanced·70 min·Testbench·3 challengesAdvancedPublishedPaid - Lab 58Memory & Reusable Blocks
Configurable PWM Generator
Generate a duty-cycle-programmable PWM from a counter compare — motor, LED and power control in one block.
Intermediate·45 min·Testbench·2 challengesIntermediatePublishedPaid
Portfolio Projects
Two complete, resume-ready builds: a UART with loopback verification and a 4-floor elevator controller.
- ProjectPortfolio Project
UART Transmitter, Receiver and Loopback Verification
A complete UART — baud generation, TX/RX FSMs and framing — verified end-to-end with a self-checking loopback.
Advanced·150 min·Testbench·3 challengesAdvancedPublishedPaid - ProjectPortfolio Project
Four-Floor Elevator Controller
A full elevator FSM — call queuing, direction decisions, door timing and safety interlocks — built and verified.
Advanced·150 min·Testbench·3 challengesAdvancedPublishedPaid
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Frequently asked questions
Are Verilog tutorials free?
Yes. The entire Verilog tutorial track remains completely free — no account or payment required. Only the hands-on labs are paid.
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No. Every Verilog lab is paid, including Lab 1. There is no free lab. You can, however, freely browse every lab's title, description, difficulty, time and concepts on this page before buying.
What does one purchase unlock?
A single purchase unlocks the complete Verilog HDL Labs package — all 58 design labs and both portfolio projects, including their full explanations, DUT code, testbenches, expected outputs, waveform guidance, solutions and challenges.
Where can I run the code?
Copy each lab's DUT and testbench into EDA Playground — a free online simulator — or any Verilog simulator you already use (e.g. Icarus Verilog, ModelSim, VCS). The code is written to run without changes.
Do labs include testbenches?
Yes. Every published lab ships with a commented, self-checking testbench so you can verify your design and see exactly what passing looks like.
Are the projects included?
Yes. Both portfolio projects — the UART with loopback verification and the four-floor elevator controller — are part of the package.
Will future labs be included?
Yes. One purchase unlocks the complete package, including any labs published later under Verilog HDL Labs. You don't pay again.
Is EDA Playground part of VLSI Mentor?
No. EDA Playground is an independent, external platform. We reference it because it's a convenient free way to run the lab code — VLSI Mentor does not host its own simulator or compiler.