DFT Design & Verification Labs.
Fifty practical Design-for-Testability labs, from the testability of a single combinational block to a DFT-enabled RTL subsystem — stuck-at faults, scan chains, fault simulation, ATPG concepts, transition-fault protocols, MBIST and logic BIST, JTAG, compression and integration verification. Every lab is an RTL simulation exercise: it teaches how DFT works, not production ATPG or silicon test signoff.
Five modules — testability to integration
DFT Fundamentals & Testability
Stuck-at faults, controllability and observability, fault injection, X propagation and test-mode isolation.
DFT-01 · DFT-02 · DFT-03 · DFT-04 · DFT-05 · DFT-06 · DFT-07 · DFT-08 · DFT-09 · DFT-10
Scan Architecture & RTL Implementation
Scan flops, chain stitching, shift and capture protocols, multiple chains and chain-integrity checking.
DFT-11 · DFT-12 · DFT-13 · DFT-14 · DFT-15 · DFT-16 · DFT-17 · DFT-18 · DFT-19 · DFT-20
ATPG, Fault Models & Coverage
Test generation, a teaching fault simulator, the D-algorithm, transition faults, LOC/LOS and coverage reporting.
DFT-21 · DFT-22 · DFT-23 · DFT-24 · DFT-25 · DFT-26 · DFT-27 · DFT-28 · DFT-29 · DFT-30
MBIST, BIST & Test Infrastructure
March tests, memory fault injection, LFSR/MISR logic BIST, signature aliasing and a reduced-scope JTAG TAP.
DFT-31 · DFT-32 · DFT-33 · DFT-34 · DFT-35 · DFT-36 · DFT-37 · DFT-38 · DFT-39 · DFT-40
Advanced DFT Integration & Verification
Multi-clock scan, test clock control, compression and X-masking, DFT assertions, debug and a capstone.
DFT-41 · DFT-42 · DFT-43 · DFT-44 · DFT-45 · DFT-46 · DFT-47 · DFT-48 · DFT-49 · DFT-50
Lab numbers are stable IDs (Lab 21 is DFT-21). Coverage figures always name the fault population they count.
All 50 labs
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Module 1DFT Fundamentals & Testability
Stuck-at faults, controllability and observability, fault injection, X propagation and test-mode isolation.
- Lab 1DFT Fundamentals & Testability
Build a Combinational Circuit and Evaluate Its Testability
Build a three-channel majority voter gate by gate, work out which internal nets each input pattern can set and observe from the pins, and watch a correct functional test miss a broken wire.
Foundation·60 min·Testbench·4 challengesFoundationPublishedPaid - Lab 2DFT Fundamentals & Testability
Detect Stuck-at-0 and Stuck-at-1 Faults
Model single stuck-at faults on named nets and find, by simulation, a vector that makes each one produce a wrong output — activation plus propagation, under the single-fault assumption.
Foundation·60 min·Testbench·4 challengesFoundationPublishedPaid - Lab 3DFT Fundamentals & Testability
Analyze Controllability and Observability in RTL
Compute SCOAP controllability and observability for the ISCAS-85 c17 circuit, measure the same properties over all 32 input patterns, and see where the estimate and the measurement disagree.
Foundation·75 min·Testbench·4 challengesFoundationPublishedPaid - Lab 4DFT Fundamentals & Testability
Design a Fault Injection Testbench
Build a testbench that forces one fault at a time onto a design copy, runs the same vectors against a fault-free golden copy, and records which faults cause a mismatch.
Foundation·75 min·Testbench·4 challengesFoundationPublishedPaid - Lab 5DFT Fundamentals & Testability
Measure Fault Coverage for a Small RTL Block
Enumerate an explicit stuck-at fault list for a small block and measure detected over total as the test set grows — stating exactly which fault population the percentage refers to — then prove one fault redundant.
Foundation·75 min·Testbench·4 challengesFoundationPublishedPaid - Lab 6DFT Fundamentals & Testability
Verify Reset and Initialization Testability
Check that every state element reaches a known value from reset, and identify flops whose uninitialised state would leave a tester comparing against X.
Foundation·60 min·Testbench·4 challengesFoundationPublishedPaid - Lab 7DFT Fundamentals & Testability
Design a Testable Register Bank
Design a small register bank with write and readback paths, and decide which control signals must be tester-controllable for every bit to be set and observed.
Foundation·60 min·Testbench·4 challengesFoundationPublishedPaid - Lab 8DFT Fundamentals & Testability
Analyze Unknown-State Propagation
Trace how an X from an unreset register spreads through, or is masked by, logic in four-state simulation, compare X optimism with X pessimism, and watch a weak checker miss an unknown that a case-equality checker catches.
Foundation·75 min·Testbench·4 challengesFoundationPublishedPaid - Lab 9DFT Fundamentals & Testability
Verify Functional and Test Mode Isolation
Add a test-mode control and verify that functional behaviour is unchanged while it is inactive, and that test-only paths cannot be activated from functional inputs.
Foundation·60 min·Testbench·4 challengesFoundationPublishedPaid - Lab 10DFT Fundamentals & Testability
Build a Mini RTL Testability Assessment
Assess a small RTL block end to end: trace its control and observation paths, measure three test plans against a defined RTL mutation population, prove the undetected mutant equivalent, and evaluate an observation-port improvement.
Foundation·120 min·Testbench·4 challengesFoundationPublishedPaid
Module 2Scan Architecture & RTL Implementation
Scan flops, chain stitching, shift and capture protocols, multiple chains and chain-integrity checking.
- Lab 11Scan Architecture & RTL Implementation
Design and Verify a Scan-Enabled D Flip-Flop
Model a mux-D scan flop behaviourally — scan enable selects scan-in over functional D — and verify both modes, noting that this is a behavioural model, not a library scan cell.
Intermediate·45 min·Testbench·4 challengesIntermediatePublishedPaid - Lab 12Scan Architecture & RTL Implementation
Convert a Register Bank into a Scan Chain
Stitch the flops of a register bank into one serial chain from scan-in to scan-out, and verify the functional design is unchanged with scan enable low.
Intermediate·60 min·Testbench·4 challengesIntermediatePublishedPaid - Lab 13Scan Architecture & RTL Implementation
Verify Scan Shift Operations
Build a reusable driver, monitor and model for an N-cell chain; measure its length, flush patterns through it, and find which defects only a non-symmetric parallel check exposes.
Intermediate·45 min·Testbench·4 challengesIntermediatePublishedPaid - Lab 14Scan Architecture & RTL Implementation
Implement Scan Capture and Shift Sequences
Drive the full load–capture–unload protocol: shift a stimulus in, pulse one functional capture clock, and shift the response out while the next pattern shifts in.
Intermediate·75 min·Testbench·4 challengesIntermediatePublishedPaid - Lab 15Scan Architecture & RTL Implementation
Design and Verify Scan Enable Control
Design the scan-enable control for the shift and capture phases, and verify it never asserts during functional operation or changes mid-shift.
Intermediate·60 min·Testbench·4 challengesIntermediatePublishedPaid - Lab 16Scan Architecture & RTL Implementation
Implement Multiple Scan Chains
Split one chain into parallel chains — equal and unequal — and verify each independently; measure shift edges per load, pad the shorter chain, and see why identical patterns cannot tell chains apart.
Intermediate·60 min·Testbench·4 challengesIntermediatePublishedPaid - Lab 17Scan Architecture & RTL Implementation
Verify Scan Chain Length and Connectivity
Measure a chain's length and cell order against its scan-chain definition with an explicit sampling convention, and find which missing, extra, broken, mis-tapped or swapped cells each check can and cannot see.
Intermediate·60 min·Testbench·4 challengesIntermediatePublishedPaid - Lab 18Scan Architecture & RTL Implementation
Build a Scan Chain Integrity Checker
Build a reusable checker that compares every unloaded bit, reports the first mismatch, classifies length, stuck and serial failures, and says when its evidence is inconclusive rather than naming a single root cause.
Intermediate·75 min·Testbench·4 challengesIntermediatePublishedPaid - Lab 19Scan Architecture & RTL Implementation
Analyze Scan Chain Timing Assumptions
Identify the timing assumptions a zero-delay scan simulation hides — hold on short scan paths, lock-up latches across clock edges — and state which need static timing analysis rather than RTL simulation.
Intermediate·60 min·Testbench·4 challengesIntermediatePublishedPaid - Lab 20Scan Architecture & RTL Implementation
Build a Parameterized Scan Register Module
Write a width-parameterised scan register that is legal and correct down to width 1, and verify load, hold, shift, priority and reset across seven widths with one reusable self-checking test module.
Intermediate·60 min·Testbench·4 challengesIntermediatePublishedPaid
Module 3ATPG, Fault Models & Coverage
Test generation, a teaching fault simulator, the D-algorithm, transition faults, LOC/LOS and coverage reporting.
- Lab 21ATPG, Fault Models & Coverage
Generate Test Vectors for Combinational Stuck-at Faults
Derive by hand, then by exhaustive search, a minimal vector set that detects every detectable single stuck-at fault of a small combinational circuit.
Intermediate·60 min·Testbench·4 challengesIntermediatePublishedPaid - Lab 22ATPG, Fault Models & Coverage
Develop a Fault Simulation Engine
Write a small serial fault simulator over a gate-level netlist description that reports which vectors detect which faults — a teaching model, not a production fault simulator.
Intermediate·120 min·Testbench·4 challengesIntermediatePublishedPaid - Lab 23ATPG, Fault Models & Coverage
Implement a Simplified D-Algorithm Exercise
Trace a bounded D-algorithm exercise on a small circuit — activation, D-frontier, non-controlling side inputs, backtrace and conflicts — and confirm every derived vector by good/faulty simulation; an exercise, not a complete D-algorithm.
Intermediate·90 min·Testbench·4 challengesIntermediatePublishedPaid - Lab 24ATPG, Fault Models & Coverage
Generate ATPG Patterns for a Sequential Scan Design
Treat scan flops as pseudo-inputs and pseudo-outputs so a full-scan design reduces to combinational test generation, then express each vector as a scan load, capture and unload.
Intermediate·90 min·Testbench·4 challengesIntermediatePublishedPaid - Lab 25ATPG, Fault Models & Coverage
Analyze Undetected and Redundant Faults
Classify every fault left undetected as redundant (untestable by construction), blocked by missing controllability or observability, or simply not yet targeted.
Intermediate·75 min·Testbench·4 challengesIntermediatePublishedPaid - Lab 26ATPG, Fault Models & Coverage
Implement Transition-Fault Test Patterns
Build two-vector tests for slow-to-rise and slow-to-fall faults under a stated cycle-based abstraction, where a transition fault means the new value arrives one cycle late — not a real path delay.
Intermediate·75 min·Testbench·4 challengesIntermediatePublishedPaid - Lab 27ATPG, Fault Models & Coverage
Verify Launch-on-Capture Test Sequences
Verify the launch-on-capture protocol — shift in V1, then two functional clocks, launch and capture, with scan enable held low — under the same cycle-based delay abstraction.
Intermediate·75 min·Testbench·4 challengesIntermediatePublishedPaid - Lab 28ATPG, Fault Models & Coverage
Verify Launch-on-Shift Test Sequences
Verify the launch-on-shift protocol, where the last shift launches the transition and scan enable must fall before the capture edge, and compare its pattern freedom with launch-on-capture.
Intermediate·75 min·Testbench·4 challengesIntermediatePublishedPaid - Lab 29ATPG, Fault Models & Coverage
Build a Fault Coverage Report Generator
Turn fault-simulation output into a report of detected, undetected, redundant and untested faults by module, with the fault population and its collapsing rule stated in the header.
Intermediate·75 min·Testbench·4 challengesIntermediatePublishedPaid - Lab 30ATPG, Fault Models & Coverage
Optimize ATPG Pattern Count
Reduce a pattern set by reverse-order fault simulation and static compaction, and show that coverage of the stated fault list is unchanged after each step.
Intermediate·75 min·Testbench·4 challengesIntermediatePublishedPaid
Module 4MBIST, BIST & Test Infrastructure
March tests, memory fault injection, LFSR/MISR logic BIST, signature aliasing and a reduced-scope JTAG TAP.
- Lab 31MBIST, BIST & Test Infrastructure
Design a March-Based Memory Test Controller
Design an FSM that walks a small behavioural RAM through a march sequence, with the address order, read/write elements and pass/fail flag defined precisely.
Advanced·90 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 32MBIST, BIST & Test Infrastructure
Verify March C- Memory Test Operations
Verify March C- exactly — ⇕(w0); ⇑(r0,w1); ⇑(r1,w0); ⇓(r0,w1); ⇓(r1,w0); ⇕(r0), 10n operations — checked element by element against the controller's memory-bus activity.
Advanced·75 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 33MBIST, BIST & Test Infrastructure
Inject Memory Faults and Verify Detection
Inject stuck-at, transition and coupling faults into a behavioural RAM model and show which ones March C- detects and which a weaker march misses.
Advanced·90 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 34MBIST, BIST & Test Infrastructure
Design a Linear Feedback Shift Register
Design Fibonacci and Galois LFSRs from a primitive polynomial and verify the maximal 2^n − 1 sequence length and the all-zero lock-up state.
Advanced·60 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 35MBIST, BIST & Test Infrastructure
Build a Pseudorandom Logic BIST Pattern Generator
Drive scan chains from an LFSR through a phase shifter and measure how fault coverage of a stated fault list grows with pattern count — and where random-pattern-resistant faults stall it.
Advanced·75 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 36MBIST, BIST & Test Infrastructure
Implement a Multiple Input Signature Register
Implement a MISR that compacts parallel responses into a signature, and verify that a single-bit response error changes the final signature.
Advanced·60 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 37MBIST, BIST & Test Infrastructure
Design a Complete Logic BIST Controller
Integrate PRPG, scan chains and MISR under a BIST controller that runs a fixed pattern count and compares the signature with a golden value from fault-free simulation.
Advanced·120 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 38MBIST, BIST & Test Infrastructure
Analyze BIST Signature Aliasing
Measure by simulation how often a faulty response stream produces the fault-free signature, and compare the rate with the ≈ 2^−n estimate for an n-bit MISR.
Advanced·75 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 39MBIST, BIST & Test Infrastructure
Implement a Simplified JTAG TAP Controller
Implement the 16-state IEEE 1149.1 TAP state machine driven by TMS and TCK, in a deliberately reduced scope: instruction register, BYPASS and IDCODE only — no boundary-scan cells.
Advanced·90 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 40MBIST, BIST & Test Infrastructure
Verify JTAG Instruction and Data Register Access
Verify IR loads and DR scans through the simplified TAP: select BYPASS and IDCODE, shift through each, and check the one-bit bypass delay and the captured ID value.
Advanced·75 min·Testbench·4 challengesAdvancedPublishedPaid
Module 5Advanced DFT Integration & Verification
Multi-clock scan, test clock control, compression and X-masking, DFT assertions, debug and a capstone.
- Lab 41Advanced DFT Integration & Verification
Design a Multi-Clock Scan Test Architecture
Organise flops from two clock domains into scan chains and decide where lock-up latches and per-domain capture clocks are needed, modelled behaviourally.
Advanced·90 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 42Advanced DFT Integration & Verification
Verify a Test Clock Controller
Verify a behavioural test clock controller that passes shift clocks, then emits a programmed pair of capture pulses, with glitch-free switching between functional and test clocks.
Advanced·90 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 43Advanced DFT Integration & Verification
Analyze Scan Chain Clock-Domain Crossing Risks
Identify where capture across asynchronous domains gives non-deterministic responses and how masking or capture-clock sequencing removes them — and state what RTL simulation cannot show.
Advanced·75 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 44Advanced DFT Integration & Verification
Design and Verify a Scan Compression Model
Build a behavioural decompressor and XOR compactor around many short internal chains, and verify that patterns loaded through a few scan pins reach the chains as intended.
Advanced·120 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 45Advanced DFT Integration & Verification
Verify X-Masking in Scan Response Compaction
Show how one X on a chain corrupts an XOR-compacted output, then add per-chain masking and verify that masked cycles no longer disturb the compared value.
Advanced·90 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 46Advanced DFT Integration & Verification
Build a DFT Assertion-Based Verification Suite
Write assertions for scan-mode invariants — scan enable stable during capture, test mode exclusive, chain output known after flush — and prove each one fires on a planted defect.
Advanced·90 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 47Advanced DFT Integration & Verification
Develop a Reusable DFT Verification Environment
Package scan load/unload tasks, a chain description and a response checker into an environment that is reused across designs by configuration, not by editing.
Advanced·120 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 48Advanced DFT Integration & Verification
Debug a Faulty Scan Architecture
Find the defects planted in a scan design — a reversed segment, a missing lock-up latch, a scan-enable glitch — from flush and capture failures alone.
Advanced·90 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 49Advanced DFT Integration & Verification
Verify Functional-to-Test Mode Integration
Verify entry into and exit from test mode — reset, clock switching, scan-enable sequencing — and that the design returns to correct functional operation afterwards.
Advanced·90 min·Testbench·4 challengesAdvancedPublishedPaid - Lab 50Advanced DFT Integration & Verification
Capstone: Design and Verify a DFT-Enabled RTL Subsystem
Take a small RTL subsystem from testability assessment through scan, a BIST block and TAP access to a coverage report with a stated fault population — a simulation-level result, not silicon test signoff.
Advanced·240 min·Testbench·4 challengesAdvancedPublishedPaid