AMBA AXI · Module 19

CPU-to-Memory Path

Trace a CPU load and store end-to-end through AXI to memory — the path from core through cache, interconnect, and memory controller, how a load becomes an AXI read burst (cache-line WRAP) and a store a write, and how outstanding transactions and cache behavior shape the real performance of the most common AXI path in any SoC.

Module 19 applies the whole curriculum to real systems, starting with the most common AXI path in any SoC: a CPU accessing memory. When a core executes a load or store, that single instruction becomes a journey through cache, interconnect, and a memory controller — and AXI is the protocol carrying it across each hop. Tracing this path concretely shows why AXI's features exist: a load miss becomes a cache-line read burst (a WRAP for critical-word-first), a store becomes a write, the interconnect routes between core and memory, outstanding transactions hide DRAM latency, and cache behavior determines whether AXI is even involved. This chapter traces a load and a store end-to-end, connecting every AXI mechanism you've learned to its role in the path every program exercises billions of times.

1. The Path: Core → Cache → Interconnect → Memory Controller

A CPU doesn't talk to memory directly — it goes through layers, and AXI connects them. The core issues loads/stores to its cache; on a miss, the cache becomes an AXI manager, issuing read/write transactions to the interconnect, which routes them (by address decode) to the memory controller (an AXI subordinate) that drives the actual DRAM. Each hop is an AXI interface, so the same transaction may cross several AXI links (core-side cache port, interconnect ports, memory-controller port), often with width and clock changes along the way.

Figure 1 — the CPU-to-memory path, hop by hop. The core issues loads/stores to its cache; on a miss the cache acts as an AXI manager to the interconnect, which decodes the address and routes to the memory controller (an AXI subordinate) driving DRAM. Each arrow is an AXI interface, so one access can cross several AXI links — the cache port, interconnect ports, and the memory-controller port — frequently with width conversion and clock-domain crossings along the way.

2. A Load Miss Becomes a Cache-Line Read Burst

Trace a load that misses the cache. The core requests one word, but the cache fetches an entire cache line (e.g. 64 bytes) — so the cache issues an AXI read burst sized to the line. It's typically a WRAP burst for critical-word-first: the requested word returns first (so the core can proceed), then the burst wraps to fill the rest of the line. The read goes out as AR (address, ARLEN for the line size, ARBURST=WRAP), and the data returns as R beats with RLAST on the final beat. This is exactly why WRAP bursts exist — the CPU load path is their canonical use.

Figure 2 — a load miss as an AXI read burst. The core requests one word; the cache misses and fetches the whole cache line via an AXI read burst — a WRAP burst (ARBURST=WRAP) sized to the line (ARLEN), for critical-word-first: the requested word returns first so the core unblocks, then the burst wraps to fill the rest of the line, with RLAST on the final beat. The CPU load-miss path is the canonical reason WRAP bursts exist.

3. A Store: Write-Back vs. Write-Through, and the Write Path

A store is more nuanced because of cache policy. In a write-back cache (the common case), the store updates the cache line and marks it dirty — no AXI traffic yet; the AXI write happens later when the dirty line is evicted (written back as a burst to memory). In a write-through cache, every store immediately issues an AXI write. Either way, the eventual write is an AXI write transaction: AW (address, length), W beats (data + WSTRB — partial for a sub-line write, full for a line write-back), and one B response. So a store may produce no AXI traffic (write-back hit), a deferred burst (eviction), or an immediate write (write-through) — cache policy decides.

Figure 3 — a store and the cache write policy. Write-back (common): the store updates the cached line and marks it dirty — no AXI traffic now; the AXI write happens later as a burst when the dirty line is evicted. Write-through: every store immediately issues an AXI write. Either way the write is AW + W beats (with WSTRB) + one B. So a store can produce no AXI traffic (write-back hit), a deferred write-back burst (eviction), or an immediate write (write-through) — the cache policy determines when AXI is involved.

4. Why Performance Depends on Outstanding and Cache Behavior

The real performance of the CPU-memory path is shaped by two things you've studied. Outstanding transactions: DRAM latency is high (tens to hundreds of cycles), so a core that issued one miss at a time and waited would stall constantly; instead, modern cores issue multiple outstanding misses (and prefetches), hiding DRAM latency behind concurrent accesses — Little's Law in action (depth ≈ bandwidth × DRAM latency). Cache behavior: most accesses hit the cache and never touch AXI at all, so AXI traffic is the miss traffic — meaning the AXI path's performance matters most under cache-miss-heavy workloads, and the cache is the first-order determinant of how much AXI traffic exists. Together, outstanding depth and hit rate determine whether the memory system keeps the core fed.

Figure 4 — what shapes CPU-to-memory performance. Cache hit rate determines how much AXI traffic exists at all (hits never touch AXI; AXI carries the miss traffic). For the misses, outstanding transactions hide DRAM latency — multiple outstanding misses/prefetches keep the path full (Little's Law: depth ≈ bandwidth × DRAM latency), so a single-miss-at-a-time core would stall but a multi-outstanding core stays fed. Together, hit rate and outstanding depth determine whether the memory system keeps the core busy.

5. Common Misconceptions

Myths to unlearn

"A CPU talks to memory directly over AXI." No — it goes through cache → interconnect → memory controller, each an AXI hop. The core itself issues loads/stores to its cache; AXI carries the miss and write-back traffic, not every instruction.
"Every load is an AXI read." Only cache misses generate AXI reads; most loads hit the cache and never touch AXI. AXI traffic is the miss traffic, so the cache hit rate is the first-order determinant of how much AXI activity exists.
"A load fetches one word over AXI." A load miss fetches an entire cache line as a read burst (typically a WRAP for critical-word-first), not one word. The CPU load path is the canonical use case for WRAP bursts.
"Every store immediately writes to memory over AXI." Only in a write-through cache. In the common write-back cache, a store marks the line dirty with no AXI traffic; the AXI write happens later on eviction. Cache policy decides when (and whether) a store hits AXI.
"DRAM latency directly limits CPU throughput." Only if you can't hide it — modern cores issue multiple outstanding misses and prefetches to overlap DRAM latency (Little's Law), so throughput can stay high despite high DRAM latency. Outstanding depth, not raw latency, is the limiter.
"The whole path runs at one width and one clock." The path typically crosses width conversions and clock-domain boundaries (core clock vs. interconnect vs. memory clock), so the AXI links along the way differ in width and clock — handled by converters and async-FIFO CDC bridges.

6. Debugging Insight

🔍 Debugging insight — locate a CPU-memory performance problem along the path

When the CPU-memory path underperforms, locate the cause by hop and by the mechanisms studied:

High miss rate / lots of AXI traffic. The first thing to check — if the cache hit rate is low, the AXI path is overloaded with miss traffic; the fix is often algorithmic/data-layout (improve locality), not AXI. AXI traffic is miss traffic, so start at the cache.
Core stalling on misses (latency-limited). Insufficient outstanding depth — the core can't issue enough concurrent misses to hide DRAM latency (Little's Law gap). Check the outstanding/MSHR depth against DRAM latency.
Read bursts not critical-word-first. If loads aren't returning the requested word first (no WRAP/critical-word-first), the core blocks longer than necessary. Check the cache's burst type and the memory controller's ordering.
Write-backs stalling reads. Eviction write traffic competing with read misses on the same path — check the interconnect's read/write arbitration and whether write-backs are deprioritized appropriately.
A hop is the bottleneck (width/clock). A width-conversion or CDC point along the path throttling throughput — apply the performance method (compute peak/actual per hop, find the narrowest).
Interconnect routing/arbitration starving the core. Under contention from other masters (DMA, GPU), the core's path may be starved — check the interconnect's QoS/arbitration.

The method: locate by hop (cache hit rate → outstanding/MSHR → burst type → write/read arbitration → width/clock hop → interconnect QoS), applying the per-mechanism diagnostics from earlier modules. The recurring first move is the cache: since AXI carries only miss traffic, the hit rate frames everything downstream.

7. Verification Insight

✅ System insight — the CPU-memory path is where every AXI mechanism earns its keep

The CPU-to-memory path is the ideal first case study because it exercises nearly every AXI mechanism in its most common real-world role, showing why each exists. Bursts — a load miss fetches a cache line as a read burst, and WRAP's critical-word-first is the reason that burst type exists; outstanding transactions — hiding DRAM latency (Little's Law, depth ≈ bandwidth × DRAM latency) so the core isn't stalled by tens-to-hundreds-of-cycle memory latency; the interconnect — decoding and routing between the core(s) and memory controller(s), with the ID remapping and arbitration of Module 12; width conversion and CDC — the path crosses width and clock boundaries (core/interconnect/memory), handled by converters and async-FIFO bridges (Module 14); WSTRB — partial writes for sub-line stores; and the read/write channels carrying loads and (eventual) stores. The system-level lessons that only emerge when you trace the full path: (1) AXI carries miss traffic, not every access — the cache hit rate is the first-order determinant of AXI activity, so memory-system performance is a cache-plus-AXI story, not AXI alone; (2) cache policy shapes the write pattern — write-back defers and batches writes (eviction bursts) while write-through streams them, so the AXI write traffic depends on policy, not just store frequency; (3) latency hiding is the whole game — DRAM is slow, and the path's performance hinges on issuing enough outstanding misses to overlap that latency, which is Little's Law applied to the most important path in the chip. For verification, this path is the canonical full-system scenario: realistic CPU traffic (mixed hit/miss, bursts, multiple outstanding, write-backs) stresses the interconnect, converters, and memory controller together, exercising the ordering, outstanding, and burst behavior that unit tests of individual blocks miss. The deeper point of starting Module 19 here is that the abstract mechanisms of Modules 1–18 become concrete and motivated when you see them in the path every program runs billions of times: WRAP bursts aren't an abstract burst type, they're how a cache line loads critical-word-first; outstanding depth isn't a tuning knob, it's how the core survives DRAM latency; the interconnect isn't a diagram, it's what connects your core to your memory. Understanding this one path deeply means understanding why AXI is designed the way it is — which is the synthesis the whole curriculum builds toward, now grounded in the most common real system. Next, we trace a different real path: a DMA engine streaming bursts into a DDR controller.

8. Interview Questions

9. Summary

The CPU-to-memory path — the most common AXI path in any SoC — runs core → cache → interconnect → memory controller → DRAM, with AXI connecting the hops (cache port, interconnect ports, memory-controller port), often across width and clock changes. Crucially, AXI carries only miss and write-back traffic, not every access: most loads/stores hit the cache and never touch AXI, so the cache hit rate is the first-order determinant of AXI activity. A load miss becomes a cache-line read burst — typically a WRAP for critical-word-first (the requested word returns first so the core unblocks, then the burst fills the line) — which is the canonical reason WRAP bursts exist. A store depends on cache policy: write-back marks the line dirty with no AXI traffic now, writing back as a burst on eviction; write-through writes immediately — so cache policy decides when (and whether) a store hits AXI.

Performance is shaped by two studied mechanisms: outstanding transactions hide high DRAM latency (Little's Law, depth ≈ bandwidth × DRAM latency — a single-miss-at-a-time core would stall, a multi-outstanding core stays fed), and cache behavior (hit rate + write policy) determines how much AXI traffic exists and when. The path exercises nearly every AXI mechanism — bursts/WRAP, outstanding, the interconnect (decode/route/ID-remap/arbitration), CDC and width conversion, WSTRB, both channel directions — in its most natural role, which is why it's the ideal first case study: it grounds the abstract mechanisms of Modules 1–18 in the concrete path every program runs, and teaches the system-level lessons (AXI = miss traffic, cache policy shapes writes, latency-hiding is the whole game) that block-level study misses. Understanding this path is understanding why AXI is designed as it is. Next, we trace a DMA engine streaming bursts into a DDR controller.

10. What Comes Next

You've traced the CPU-memory path; next, a different real traffic pattern:

19.2 — DMA-to-DDR Transfers (coming next) — tracing a DMA engine's burst stream landing in a DDR controller, a throughput-oriented path that contrasts with the latency-sensitive CPU path.

Previous: 18.8 — Tricky Misconceptions. Related: 7.4 — WRAP Bursts for the cache-line fetch, 8.1 — Why Outstanding Transactions for DRAM latency hiding, and 12.1 — AXI Interconnect Overview for the routing between core and memory.