AMBA AXI · Module 7

WRAP Bursts

The AXI WRAP burst (AxBURST=10) — addresses increment then wrap within an aligned block. Why this is the natural fit for critical-word-first cache-line fills, the wrap-boundary math, and the strict length/alignment constraints.

The third and most specialized burst type is WRAP (AxBURST = 2'b10). It addresses like INCR — stepping forward by 2^AxSIZE each beat — but with a twist: when the address reaches the top of an aligned block, it wraps back to the block's lower boundary and continues. That behavior exists for one dominant purpose: critical-word-first cache-line fills, where a CPU gets the exact word it stalled on first, then the rest of the line streams in, wrapping around to cover the words before it. This chapter covers the wrap mechanism, the boundary math, a fully worked example, and WRAP's strict constraints.

1. What a WRAP Burst Is

A WRAP burst increments like INCR, but the address is confined to an aligned block whose size is the total burst size. When the incrementing address would step past the block's upper edge, it wraps to the block's lower (aligned) boundary and keeps going until all AxLEN+1 beats are done. So the set of addresses touched is fixed (the whole aligned block), but the order starts at AxADDR — which can be in the middle of the block — and wraps around.

The block size — and thus the wrap point — is:

wrap block size (bytes) = (AxLEN + 1) × 2^AxSIZE (burst length × bytes per beat)

and the block is aligned to that size. The address wraps at the block's upper boundary: it counts up by 2^AxSIZE, and when it reaches lower_boundary + block_size, it returns to lower_boundary.

Figure 1 — a WRAP burst (AxBURST=10) over a 4-beat, 4-byte block (16 bytes, aligned to 0x00–0x0F). Starting at the critical word 0x08, the address steps 0x08 → 0x0C, then WRAPS at the block top back to 0x00 → 0x04. All four words of the block are covered, but the order begins at the requested word and wraps around.

2. The Wrap Math, Worked

Take the canonical example: 4-beat WRAP (AxLEN = 3), 4 bytes/beat (AxSIZE = 2), starting at AxADDR = 0x08.

Block size = (3+1) × 4 = 16 bytes → the aligned block is 0x00–0x0F (0x08 rounded down to a 16-byte boundary is 0x00).
Lower boundary = 0x00; upper boundary = 0x10.
Beats step by 4: start 0x08 → 0x0C. Next step would be 0x10, which hits the upper boundary, so it wraps to 0x00 → then 0x04.
Order: 0x08, 0x0C, 0x00, 0x04 — the critical word 0x08 first, all four words of the line covered.

In general: lower = AxADDR − (AxADDR mod block_size); each beat is lower + ((AxADDR + n·2^AxSIZE − lower) mod block_size). The full derivation across all burst types is Chapter 7.5; the takeaway here is that WRAP visits the entire aligned block but starts at the requested word and wraps.

3. A WRAP Read on the Wire

The same example as a read — the CPU requested 0x08, and the line streams back in wrap order:

wrap-burst — 4-beat WRAP read, critical word 0x08 first

6 cycles

Figure 2 — wrap-burst: a 4-beat WRAP read (AxLEN=3, ARBURST=10, AxSIZE=2) starting at the critical word 0x08. The R beats return 0x08, 0x0C, then wrap to 0x00, 0x04 — RLAST on the fourth. The CPU receives the word it stalled on (0x08) in beat 0 and can resume before the rest of the line arrives.

4. Why WRAP Exists — Critical-Word-First Cache Fills

The motivation is cache-line fill latency. When a CPU misses the cache on some word, it must fetch the whole line — but it only stalled on one specific word, which may sit anywhere in the line. With a WRAP burst, the fill starts at the exact word the CPU needs (the critical word), returns it in the first beat so the CPU can resume immediately, then continues and wraps to fetch the rest of the line. The cache still gets a complete, contiguous line (the whole aligned block); the CPU just doesn't wait for the words before the critical one.

An INCR fill would have to either start at the line base (delaying the critical word until its position in the line) or only fetch from the critical word to the line end (leaving the line incomplete). WRAP solves both: critical word first and a full line, in one transaction. This is why WRAP's length is tied to power-of-two cache-line sizes and its block is aligned — it mirrors how caches are organized.

Figure 3 — critical-word-first fill. On a cache miss for a word mid-line, a WRAP burst returns that critical word in beat 0 so the CPU resumes immediately, then wraps to fill the remaining words of the aligned line. One transaction delivers both low latency (critical word first) and a complete contiguous line.

5. Constraints

WRAP is the most constrained burst type:

Length ∈ 16. A WRAP burst must be exactly 2, 4, 8, or 16 beats — a power of two. No other lengths are legal (so AxLEN ∈ 15).
Aligned start. AxADDR must be aligned to the transfer size (2^AxSIZE). WRAP does not permit the unaligned starts that INCR allows — the wrap math depends on size-aligned addressing.
Block aligned to total size. The wrap block is aligned to (AxLEN+1) × 2^AxSIZE, which is why the wrap boundary is well-defined.
No 4 KB crossing concern in practice. Since a WRAP burst is confined to its aligned block (at most 16 × 128 bytes, and cache lines are far smaller), it stays within one aligned region and never approaches a 4 KB boundary the way a long INCR can.

Figure 4 — WRAP's constraints. Length must be 2/4/8/16 beats; the start address must be aligned to the transfer size; and the burst is confined to an aligned block of (AxLEN+1)·2^AxSIZE bytes within which it wraps. These rules tie WRAP to power-of-two, aligned cache lines.

6. Common Misconceptions

7. Debugging Insight

🔍 Debugging insight — WRAP bugs are wrap-point and ordering errors

WRAP defects center on the wrap boundary and beat ordering:

Cache line filled with the wrong word order / wrong wrap point? The block size or alignment is miscomputed — the wrap boundary is (AxLEN+1)·2^AxSIZE-aligned. If the slave/monitor wraps at the wrong address, the words land in the wrong line positions. Recompute lower = AxADDR − (AxADDR mod block_size) and check where the wrap actually happened.
Address never wraps (runs off the top like INCR)? The target is treating a WRAP as INCR — AxBURST decoding is wrong, or the wrap logic is missing. Beats past the block top spill into the next block instead of wrapping to the base.
A WRAP burst with length 3, 5, or unaligned start rejected/misbehaving? Those are illegal — WRAP must be 2/4/8/16 beats with a size-aligned start. A master generating an illegal WRAP is the bug.
Critical word not first? The burst started at the line base instead of the requested word — the fill logic isn't passing the critical address as AxADDR. WRAP's benefit is lost (correctness may be fine, latency isn't).

Triage: compute the expected wrap order (0x08, 0x0C, 0x00, 0x04 for the canonical case) and compare; an order/position mismatch is a wrap-boundary error, a run-off-the-top is a WRAP-treated-as-INCR error, and an illegal length/alignment is a malformed-burst error.

8. Verification Insight

✅ Verification insight — wrap ordering, legality, and full-block coverage

WRAP verification is about the wrap arithmetic and legality. Assert the per-beat addresses follow the wrap formula — lower + ((AxADDR + n·2^AxSIZE − lower) mod block_size) — so the reference model knows the exact (wrapped) order and a byte-accurate scoreboard confirms each beat's data lands at the right line position; this catches both wrong wrap points and run-off-the-top (WRAP-as-INCR) bugs. Enforce legality: length ∈ 16 and AxADDR aligned to 2^AxSIZE — flag any other length or an unaligned WRAP start as a protocol violation. Confirm the burst covers the entire aligned block exactly once (no skipped or repeated address).

Coverage should sweep all four legal lengths, start addresses at every offset within the block (so the wrap happens at each possible position — including the aligned-base case where WRAP degenerates to INCR-like order, and the worst case where the critical word is at the block top), and the relevant cache-line sizes. The most valuable directed tests put the start at a non-base offset and verify both the critical-word-first ordering and the complete line — that's the behavior WRAP exists to provide, and the part INCR-style logic gets wrong. Address-progression derivations for all types are consolidated in Chapter 7.5.

9. Interview Questions

10. Summary

The WRAP burst (AxBURST = 2'b10) increments like INCR but wraps within an aligned block: the address steps by 2^AxSIZE, and on reaching the block's upper boundary it returns to the lower boundary. The block is (AxLEN+1) × 2^AxSIZE bytes, aligned to that size, and the burst covers it exactly once — starting at AxADDR (which may be mid-block) and wrapping. The canonical 4-beat/4-byte burst from 0x08 visits 0x08, 0x0C, 0x00, 0x04. WRAP exists for critical-word-first cache-line fills: the CPU's needed word comes back in beat 0 so it resumes immediately, while the burst wraps to deliver the complete line in one transaction. Its constraints are strict — length ∈ 16 and a size-aligned start — because the wrap math and the cache geometry demand it.

WRAP's bugs are ordering, not data: wrong wrap points, treating WRAP as INCR (running off the block top), illegal lengths/alignments, or corrupted lines assembled from correct beats placed in the wrong slots. Debug and verify by reconstructing the wrap order from (AxLEN+1)·2^AxSIZE and AxADDR and checking each beat's position, not just its data. Next: a single chapter that consolidates the per-beat address calculation for all three burst types with worked examples — the arithmetic behind FIXED, INCR, and WRAP in one place.

11. What Comes Next

You've seen all three burst types; next, the arithmetic that ties them together:

7.5 — Burst Address Calculation (coming next) — worked per-beat address derivations for FIXED, INCR, and WRAP, including unaligned and wrap cases.
7.6 — The 4KB Boundary Rule (coming soon) — why a burst must not cross a 4 KB boundary, and how to split.

Previous: 7.3 — INCR Bursts. Related: 6.2 — AxBURST for the burst-type selector. For the broader protocol catalog, see the AMBA family overview doc.