Strongly-typed HDL exercises that walk from your first entity/architecture pair up to reusable packages and parameterised IP.
VHDL rewards engineers who respect its type system. These labs make that discipline pay off — each one ends with synthesizable RTL plus a deliberate observation about contract, conversion, or generic reuse.
Model a simple half-adder using strict entity/architecture separation and instantiate it inside a test wrapper.
Build a 4-bit ALU slice with `when/else` and `with/select` and contrast both forms.
Demonstrate why an incomplete sensitivity list silently desynchronises simulation from synthesis.
Model a D flip-flop with async reset and prove it infers a single FF in synthesis.
Parameterise a counter using a `generic` and instantiate three widths from one entity.
Model a Moore FSM using an enumerated state type and prove the state graph is bisimilar to the spec.
Bundle a bus interface into a `record` inside a `package` and reuse it across master, slave and monitor.