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Learnings · Verilog HDL · Labs

Verilog labs.

Hands-on, synthesizable-by-default labs. Each lab is small enough to finish in a focused session and ships with a deliverable you can show in a code review.

0of 7 labs live4 phases · grouped by difficulty
Lab Philosophy

Small, working pieces of silicon-grade code.

Every lab targets one engineering intuition — never just syntax. You build the circuit, prove it behaves on a waveform, then explain its synthesis output. Done well, the seven labs collapse the gap between reading RTL and writing it.

Lab Roadmap

4-phase progression.

  1. 01Combinational2
  2. 02Storage2
  3. 03Sequential2
  4. 04Control1

All Labs

Grouped by difficulty

Foundation

3 labs
  1. Lab 01

    Designing of Logic Gates

    Model AND, OR, NAND, NOR, XOR, XNOR three ways — gate primitives, dataflow assigns, and behavioural always blocks.

    Skills practiced
    • Gate primitives
    • Continuous assignment
    • Behavioural style
    Deliverable
    A reusable gate library with self-checking testbench and a comparison of the three modeling styles.
    FoundationPlannedCombinational
  2. Lab 02

    Designing of Combinational Circuits

    Build adders, encoders, decoders, multiplexers and comparators with clean `always @*` style.

    Skills practiced
    • always @*
    • Default assignments
    • Case vs if-else
    Deliverable
    A small combinational IP block (4-bit ALU slice) that lints zero-latch and synthesises predictably.
    FoundationPlannedCombinational
  3. Lab 03

    Designing of Different Types of Latches

    SR, D, gated D and JK latches modeled intentionally and accidentally — with a debugging lab on each.

    Skills practiced
    • Level-sensitive logic
    • Latch inference
    • Linting
    Deliverable
    A waveform-annotated report distinguishing intentional latches from inferred ones in incomplete RTL.
    FoundationPlannedStorage

Intermediate

3 labs
  1. Lab 04

    Designing of All Flip-Flops

    D, T, JK and SR flip-flops with sync/async reset variants — written the way RTL teams ship them.

    Skills practiced
    • Non-blocking assignments
    • Reset strategies
    • Sequential RTL
    Deliverable
    A flip-flop library plus a synthesis-vs-simulation comparison for each reset variant.
    IntermediatePlannedStorage
  2. Lab 05

    Designing of Different Types of Counters

    Binary, BCD, ring, Johnson, up/down and programmable counters with enable, load and synchronous reset.

    Skills practiced
    • Counter topologies
    • Modulo arithmetic
    • Decode-speed trade-offs
    Deliverable
    A parametric counter IP with a coverage report against load/enable corner cases.
    IntermediatePlannedSequential
  3. Lab 06

    Designing of Multiple Shift Registers

    SISO, SIPO, PISO, PIPO and universal shift registers — including the loadable, bidirectional variant.

    Skills practiced
    • Serial datapaths
    • Parameterisation
    • Bidirectional shifting
    Deliverable
    A single parameterised universal shift register that swaps between all five modes from a control word.
    IntermediatePlannedSequential

Advanced

1 lab
  1. Lab 07

    Designing of Pattern Detector FSM

    Mealy and Moore pattern detectors for overlapping and non-overlapping sequences.

    Skills practiced
    • State encoding
    • Mealy vs Moore
    • FSM lint cleanliness
    Deliverable
    Two equivalent FSMs (Mealy & Moore) detecting the same sequence, with a waveform showing timing differences.
    AdvancedPlannedControl