GLS · Topic
Gate-Level Simulation Debug Methodology
A systematic order for gate-level debug — zero-delay first, then unit delay, then full timing, and what each stage can and cannot prove.
Gate-level debug goes wrong when it starts at the end. A netlist that fails with full timing annotated has many possible causes, and most of them are not timing: a connectivity error, an X from reset, a testbench that assumed RTL behaviour. Running zero-delay first isolates function from timing, and unit delay isolates ordering from delay values — so by the time full timing runs, most candidate causes are already eliminated.