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GLS · Chapter 12 · GLS Debug Methodology

Common GLS Mistakes & How to Avoid Them

This catalog collects the recurring gate-level simulation mistakes from across the book and pairs each with the practice that avoids it. They fall into a handful of families: running zero-delay because no SDF was annotated, treating an expected unknown from corruption, a notifier, or a crossing as a logic bug, testbench-induced violations from edge-aligned stimulus or edge sampling, using the wrong timing corner, disabling checks wholesale to quiet a log, missing or mis-controlled reset, dismissing a GLS unknown because RTL looked clean, treating GLS as a timing, CDC, or coverage signoff, broken hierarchical references after synthesis, and fixing downstream symptoms instead of the first divergence. Each entry gives a fast tell and a known fix, so you can run down the list whenever a gate-level run surprises you. It closes the debug-methodology chapter.

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Chapter 12 · Section 12.6 · GLS Debug Methodology

Project thread — this catalog distills every accuracy rule and pitfall from the counter through the mini-SoC into one field guide. It closes the debug chapter; Chapter 13 turns to making GLS affordable (performance & regression).

1. Why Should I Learn This?

Most gate-level grief comes from a short list of recurring mistakes — knowing them is a shortcut.

  • Each has a fast tell and a known avoidance.
  • Half are misreading a modelling behavior as a bug (expected X).
  • Half are misusing GLS (no SDF, wrong corner, treating it as signoff).

Run this list when a gate-level run surprises you — it short-circuits the funnel (12.1).

2. Real Silicon Story — five mistakes in one run

A single gate-level regression hit five of these at once: it ran zero-delay (no SDF), its testbench sampled at the clock edge, it used the wrong corner, someone disabled checks to quiet the log, and a corruption X was being debugged as a logic bug.

Each was a known mistake with a known fix. Running the catalog — annotate SDF, sample on a strobe, use the right corner, re-enable and triage checks, recognize the expected corruption X — cleared the whole mess in an afternoon. No one bug was hard; the run had simply accumulated familiar mistakes.

Lesson: gate-level runs fail in recurring, recognizable ways. A catalog of mistakes-and-avoidances resolves most surprises fast — recognize the pattern, apply the known fix.

3. Concept — the catalog

A. Setup / usage mistakes (misusing GLS):

  • No SDF → silent zero-delay. Avoid: annotate an SDF and read the coverage log (0 unmatched); label the run's timing mode (4.3/4.5).
  • Wrong corner. Avoid: setup → slow/MAX, hold → fast/MIN; match models/SDF to the corner (3.4/4.4).
  • Broken hierarchical references after synthesis. Avoid: reference ports, use bind, preserve needed signals (5.2).
  • Treating GLS as a signoff it isn't. Avoid: STA signs off timing (0.3), static CDC/MTBF verify CDC (9.1), ATPG measures coverage (11.1) — GLS is dynamic/functional.

B. Misreading modelling as a bug (expected X):

  • Corruption X on power-down (10.2), notifier X from a timing check (8.5), crossing / metastability-risk X (9.2). Avoid: recognize these as expected modelling — check isolation/retention/sequencing (power), triage real-vs-artifact (timing), check the crossing structure (CDC) — not the logic.

C. Testbench mistakes:

  • Edge-aligned stimulus → TB-induced violations (5.3); sampling at the clock edge → false mismatch (5.4). Avoid: drive a skew after the edge; strobe after settling; handle X explicitly.
  • Reset not applied / test-mode reset mis-controlled (7.x/11.5). Avoid: apply a proper reset before comparing; use the correct test-mode reset.

D. Judgment mistakes:

  • Disabling checks wholesale to quiet a log (8.4). Avoid: triage each firing; disable only specific, justified artifacts — never all.
  • 'RTL is golden' for X (dismissing a GLS X) (6.4/12.5). Avoid: judge by source — RTL-optimism can hide a real bug a GLS X exposes.
  • Fixing downstream symptoms instead of the first divergence (12.2); leaving debug forces in (12.4). Avoid: fix the first divergence at the source; remove all forces.

The meta-rule:

  • Almost every mistake is either misusing GLS (A) or misreading a modelling behavior as a bug (B) or a testbench/judgment slip (C/D) — the funnel's real-vs-artifact question (12.1) catches most of them.

Scope (accuracy): this catalog synthesizes every accuracy rule in the book; GLS stays dynamic (0.3).

Four families of GLS mistakes: misusing GLS, misreading modelling as a bug, testbench mistakes, judgment mistakesask real-vs-artifact (12.1)askreal-vs-artifac…funnel catchesmostA. Misusing GLSno SDF (4.5) · wrong corner(3.4) · hier refs (5.2) ·treating as signoffB. Misreadingmodellingexpected X: corruption(10.2) · notifier (8.5) ·crossing (9.2)C. Testbenchedge stimulus (5.3) · edgesampling (5.4) · reset(7/11.5)D. Judgmentdisable checks (8.4) · RTL-golden-for-X (6.4) · symptoms not first div (12.2) · forces left in (12.4)disable checks (8.4) ·RTL-golden-for-X (6.4) ·symptoms not first div…12
Figure 1 - the common-GLS-mistakes catalog (representative). Four families: (A) MISUSING GLS -- no SDF/zero-delay (4.5), wrong corner (3.4), broken hier refs (5.2), treating GLS as signoff (STA/static-CDC/ATPG). (B) MISREADING MODELLING AS A BUG -- expected X: corruption (10.2), notifier (8.5), crossing/metastability-risk (9.2). (C) TESTBENCH -- edge-aligned stimulus (5.3) / sampling (5.4), reset not applied (7/11.5). (D) JUDGMENT -- disabling checks wholesale (8.4), 'RTL golden' for X (6.4), fixing symptoms not first divergence (12.2), leaving forces in (12.4). The funnel's real-vs-artifact question (12.1) catches most.

4. Mental Model — a pre-flight checklist for gate-level runs

This catalog is a pilot's pre-flight checklist — a list of known failure points you run down before (and when) something looks wrong.

  • Pilots don't rediscover how planes fail each flight — they check the known list (fuel, flaps, instruments).
  • Gate-level engineers shouldn't re-derive each surprise — run the catalog: SDF annotated? right corner? expected X? testbench timing-aware? checks triaged not disabled? judging by source? first divergence?
  • Most 'surprises' are a checklist item you can tick to a known fix — fast, boring, reliable.

Run the checklist; don't improvise a crash investigation each time.

5. Working Example — the catalog applied

Running the catalog against a surprising run (tool-neutral):

Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
# Common-GLS-mistakes catalog - REPRESENTATIVE (tool-neutral) - run this when a run surprises you:
# A. MISUSING GLS
#   [ ] SDF annotated? coverage log 0 unmatched? (else silent zero-delay, 4.5)
#   [ ] right corner? setup=slow/MAX, hold=fast/MIN (3.4/4.4)
#   [ ] hierarchical refs via ports/bind/preserved? (5.2)
#   [ ] not treating GLS as signoff (STA=timing, static-CDC/MTBF=CDC, ATPG=coverage)
# B. EXPECTED X (modelling, not a bug)
#   [ ] corruption X on power-down (10.2)? notifier X (8.5)? crossing/metastability-risk X (9.2)?
# C. TESTBENCH
#   [ ] stimulus a skew AFTER the edge (5.3)? strobe AFTER settle + handle X (5.4)? proper reset (7/11.5)?
# D. JUDGMENT
#   [ ] triaged checks (not disabled wholesale, 8.4)? judged X by SOURCE not 'RTL golden' (6.4)?
#   [ ] fixed the FIRST divergence (12.2)? removed all debug forces (12.4)?

Practical context (representative, tool-neutral):

Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
# When to run the catalog (tool-neutral):
#   BEFORE a run: A (SDF/corner/refs/signoff-scope) - set it up right
#   WHEN a run surprises you: B (expected X?) then C (testbench?) then D (judgment?)
#   meta-rule: almost every item reduces to the funnel's REAL-vs-ARTIFACT question (12.1)
#   most 'bugs' are: no SDF, an expected X read as a bug, a testbench timing slip, or a judgment error

A catalog mistake (edge sampling) vs its avoidance (strobe), as a real waveform:

A catalog mistake and its fix: edge sampling reports a false mismatch; strobing after settle reads correctly

8 cycles
Sampling at the clock edge reads the old value (false mismatch); sampling on a strobe after settling reads the correct valueedge sample → old value (mistake)edge sample → old valu…strobe after settle → correct (fix)strobe after settle → …clkoutstrobe (after settle)t0t1t2t3t4t5t6t7
Representative — one catalog entry (C: testbench). out updates a clk-to-Q delay after the edge. A checker sampling AT the edge reads the old value (false mismatch, 5.4); the avoidance is to sample on a STROBE after settling, reading the correct value. Each catalog entry pairs a recognizable mistake with a known avoidance — run the list when a gate-level run surprises you.

6. Debugging Session — a run that hit several catalog mistakes at once

1

A gate-level run hits several catalog mistakes at once (no SDF, edge sampling, wrong corner, disabled checks, an expected corruption X debugged as logic); running the catalog and applying each known avoidance resolves the whole mess quickly

RUN THE CATALOG: RECOGNIZE THE MISTAKE, APPLY THE KNOWN AVOIDANCE
Symptom

A gate-level regression is a mess — mismatches, Xs, and violations everywhere — and it looks like many hard bugs.

Root Cause

Several familiar catalog mistakes at once, not many hard bugs. Running the catalog reveals: the run is zero-delay because no SDF was annotated (A, 4.5); the checker samples at the clock edge → false mismatches (C, 5.4); it uses the wrong corner (A, 3.4); someone disabled checks to quiet the log, masking real ones (D, 8.4); and a corruption X on power-down is being debugged as a logic bug when it's expected modelling (B, 10.2). Each is a known mistake with a fast tell and a known avoidance — the run simply accumulated them. The 'many hard bugs' impression comes from not recognizing the recurring patterns; almost every item reduces to the funnel's real-vs-artifact question (12.1).

Fix

Run the catalog and apply each avoidance: (A) annotate an SDF (verify coverage, 4.5) and use the right corner (3.4); (C) strobe after settling (5.4) and drive stimulus clear of the edge (5.3); (D) re-enable and triage the checks (8.4) and, for the Xs, judge by source (6.4); (B) recognize the corruption X as expected power-down modelling (10.2) — check isolation/retention/sequencing, not the logic. What looked like many hard bugs collapses into a handful of recognized mistakes with known fixes. The lesson: gate-level runs fail in recurring, recognizable ways — misusing GLS (no SDF, wrong corner, broken refs, treating it as signoff), misreading expected X as a bug (corruption/notifier/crossing), testbench slips (edge stimulus/sampling, reset), and judgment errors (disabling checks, 'RTL golden' for X, fixing symptoms, leaving forces in); run the catalog, recognize the pattern, apply the known avoidance, and let the funnel's real-vs-artifact question (12.1) catch most. (This synthesizes the book's accuracy rules; GLS stays dynamic, 0.3.)

7. Common Mistakes

  • Re-deriving each surprise instead of running the catalog.
  • Not asking real-vs-artifact (12.1) — most items reduce to it.
  • Treating a messy run as many hard bugs — usually a few recurring mistakes.
  • Fixing without recognizing the pattern — the known avoidance is faster.
  • Skipping the pre-run checklist (A) — set the run up right first.

8. Industry Best Practices

  • Run the catalog before a GLS run (A) and when one surprises you (B/C/D).
  • Recognize the recurring families — misuse, expected-X, testbench, judgment.
  • Apply the known avoidance for each — most have a one-line fix.
  • Lean on real-vs-artifact (12.1) — it catches most catalog items.
  • Keep the catalog as a team checklist — shared, reviewed, updated.

Senior Engineer Thinking

  • Beginner: "This run has a dozen hard bugs."
  • Senior: "Or a few familiar mistakes. Is SDF annotated? Right corner? Any expected X (corruption/notifier/crossing)? Sampling on a strobe? Checks triaged not disabled? Judging by source? I run the catalog — most 'bugs' are recognized items."

The senior recognizes recurring mistakes and applies known avoidances instead of treating each run as novel.

Silicon Impact

A catalog of recurring mistakes is a force multiplier: it turns most gate-level surprises into recognized items with known fixes, cutting debug time from days to hours and — critically — preventing the dangerous mistakes from shipping bugs. The high-stakes entries are the ones that mask real problems: disabling checks wholesale (8.4) or dismissing a GLS X as 'RTL is golden' (6.4) can hide a real bug that reaches silicon (0.3); no SDF (4.5) makes a 'timing' run meaningless; a left-in force (12.4) makes a broken design look fixed. Running the catalog — especially the funnel's real-vs-artifact question (12.1) — is what keeps these from slipping through. This closes the book's debug arc: the funnel (12.1), first-divergence (12.2), waveform trace (12.3), force/confirm (12.4), RTL-vs-GLS (12.5), and this catalog together make gate-level debugging systematic, fast, and honest — the foundation for running GLS at scale (Chapter 13).

Engineering Checklist

  • (A) SDF annotated (coverage OK), right corner, refs via ports/bind, GLS not treated as signoff.
  • (B) Recognized expected X (corruption/notifier/crossing) as modelling, not a bug.
  • (C) Stimulus a skew after the edge, strobe after settling, proper reset.
  • (D) Checks triaged (not disabled wholesale), X judged by source, first divergence fixed, forces removed.
  • Ran the catalog and applied the known avoidance for each item.

Try Yourself

  1. Take a messy gate-level run and, instead of debugging signal-by-signal, run the catalog (A→B→C→D).
  2. Observe: several 'bugs' are recognized mistakes — no SDF, edge sampling, wrong corner, an expected X.
  3. Change: apply the known avoidance for each (annotate SDF, strobe, right corner, recognize the expected X).
  4. Expect: the mess collapses into a handful of resolved items — far faster than one-by-one. Keep the catalog as your default checklist.

The catalog is a discipline, tool-independent. No paid tool required.

Interview Perspective

  • Weak: "Every gate-level run has different, hard bugs."
  • Good: "Gate-level runs fail in recurring ways — no SDF, wrong corner, testbench timing, expected Xs."
  • Senior: "There's a short catalog: misusing GLS (no SDF, wrong corner, broken refs, treating it as signoff), misreading expected X (corruption/notifier/crossing) as a bug, testbench slips (edge stimulus/sampling, reset), and judgment errors (disabling checks, 'RTL golden' for X, symptoms over first-divergence, forces left in). I run the catalog, recognize the pattern, and apply the known avoidance — and most reduce to the real-vs-artifact question."

9. Interview / Review Questions

10. Key Takeaways

  • Gate-level runs fail in recurring, recognizable ways — a catalog of mistakes-and-avoidances resolves most surprises fast (recognize the pattern → apply the known fix).
  • Four families: (A) misusing GLS (no SDF/zero-delay 4.5, wrong corner 3.4, broken refs 5.2, treating GLS as signoff it isn't — STA/static-CDC/ATPG); (B) misreading expected X as a bug (corruption 10.2, notifier 8.5, crossing/metastability-risk 9.2); (C) testbench (edge stimulus 5.3 / sampling 5.4, reset 7/11.5); (D) judgment (disabling checks 8.4, 'RTL golden' for X 6.4, symptoms over first-divergence 12.2, forces left in 12.4).
  • The most dangerous mistakes mask real bugs — disabling checks wholesale (8.4), dismissing a GLS X (6.4), no SDF (4.5), a left-in force (12.4) — producing false confidence.
  • Almost every item reduces to the funnel's real-vs-artifact question (12.1) — run the catalog before a run (A) and when surprised (B/C/D).
  • This closes the book's debug arc — funnel (12.1), first-divergence (12.2), waveform trace (12.3), force/confirm (12.4), RTL-vs-GLS (12.5), and this catalog make gate-level debug systematic, fast, and honest; GLS stays dynamic (0.3). This closes Chapter 12; next, Chapter 13 makes GLS affordable (performance & regression strategy).

Quick Revision

GLS runs fail in recurring ways - run the CATALOG. (A) Misusing GLS: no SDF/zero-delay (4.5), wrong corner (3.4), broken refs (5.2), treating as signoff (STA/static-CDC/ATPG). (B) Expected X as a bug: corruption (10.2), notifier (8.5), crossing (9.2). (C) Testbench: edge stimulus (5.3)/sampling (5.4), reset (7/11.5). (D) Judgment: disable checks (8.4), 'RTL golden' for X (6.4), symptoms not first-divergence (12.2), forces left in (12.4). Most reduce to real-vs-artifact (12.1); the masking ones are most dangerous. Chapter 12 complete; next: Chapter 13 - performance & regression.