Why Scan Exists

Chapter 3 · Section 3.1 · Scan Architecture

Project thread — 2.6 showed the flop's faults are unreachable when embedded. This chapter builds scan to reach them; 3.6 makes the counter fully scannable and detects a fault end-to-end.

1. Why Should I Learn This?

Scan is the foundation of all structural test — every later chapter (insertion, ATPG, coverage, compression) assumes it.

• Scan makes every flop controllable (load any state) and observable (read any state).
• That collapses the sequential test problem into a combinational one — the key to tractable ATPG.
• Without scan: functional test only → low coverage → huge escapes.
• Cost: a mux per flop (area + path delay), scan pins, test power — worth it, so full scan is the default.

2. Real Silicon Story — the functional-test coverage ceiling

A team tried to test a state-heavy block using functional patterns only — long, hand-and-simulation-crafted sequences meant to walk the design through interesting states. They poured weeks into more sequences, chasing coverage.

Coverage plateaued far below target. The problem wasn't the patterns' cleverness — it was fundamental: reaching a specific deep internal state required steering the design through many precise clock cycles, and observing an internal node required propagating its effect through more cycles to an output. Most faults sat on state that was practically unreachable in a bounded number of functional cycles — the sequential-depth wall.

Switching to full scan dissolved the wall overnight. The same faults became trivially reachable: load the exact state through the chain, capture once, read the state out. Coverage jumped to target. Lesson: functional test fights an exponential sequential problem; scan makes it combinational, and that's why it's non-negotiable for real coverage.

3. Factory Perspective — what scan means to each role

• What the test engineer sees: a loadable/observable design — patterns become shift-in stimulus + one capture + shift-out response (3.3), and coverage becomes achievable.
• What the yield engineer sees: that structural scan test sorts defective dies with high coverage, so defects are caught instead of escaping — the basis of a binnable, diagnosable flow.
• What the RTL/DV engineer sees: that their flops will be swapped to scan cells, so scan-friendly discipline (synchronous design, controllable resets/clocks) matters — and that a mux delay lands in their functional timing path.
• What management cares about: scan is an area/timing/pin cost that buys the coverage (and DPPM, 1.5) commitment — a methodology decision (full scan) made up front, not a late patch.

4. Concept — controllability, observability, and the sequential→combinational collapse

The two properties scan grants (to every flop):

• Controllability: the ability to set a node to a chosen value. Scan gives full controllability of state — shift any pattern into the flops.
• Observability: the ability to see a node's value at an output. Scan gives full observability of state — shift the captured values out.
• Recall 2.2: detection = excite + propagate. Scan supplies both for state — you excite by loading, propagate by capturing-and-observing.

The transformation (the deep idea):

• Without scan (sequential): flops' values depend on a history of clock cycles. To place the circuit in a target state, ATPG must find an input sequence over time (justification through many cycles); to observe a fault, it must propagate over many cycles to an output. This search is exponential in sequential depth — intractable for real designs.
• With full scan (combinational): in shift mode you load state directly (no navigation), then a single capture exercises the combinational logic between flops, then you shift the response out. ATPG now only solves a combinational problem for one cycle — well-understood and tractable — treating flop outputs as pseudo-primary-inputs and flop inputs as pseudo-primary-outputs.

The honest cost (don't hand-wave):

• Area: a 2:1 mux (and control routing) per flop — commonly a few percent of chip area (design-dependent, representative).
• Timing: the mux adds delay in the functional D path — a real timing budget item.
• Pins: dedicated scan-in / scan-out / scan-enable (mitigated later by compression, Ch7).
• Test power: many flops toggle simultaneously during shift → shift-power management matters.

Why full scan won:

• Partial scan (scanning only some flops) saves area but leaves sequential depth → lower, harder coverage.
• Functional test alone hits the sequential wall (the story). Full scan's tractable, high coverage made it the default.

5. Mental Model — a save/load button for the whole chip

Imagine a video game whose deep levels take hours of precise play to reach (sequential depth). Testing 'does level 47 work?' by playing there every time is hopeless.

• Scan is a save/load system for every piece of game state. You load any level instantly (controllability) and read the full game state instantly (observability) — no playing through.
• Now testing level 47 is trivial: load the exact state, take one action (capture), read the result — you never navigate the hours of play.
• The combinational logic between flops is that 'one action'; scan removes the hours of navigation (sequential time) around it.
• The cost of adding save/load hooks everywhere is real (a bit of overhead in every state slot — the mux per flop), but it turns an impossible test job into an easy one.

You don't test a deep level by playing to it — you load it. Scan is the chip's load button.

6. Working Example — the coverage collapse, without vs with scan

Contrast the two regimes on a state-heavy block (the counter is the concrete case in 3.6):

# Sequential (no scan) vs full scan — REPRESENTATIVE, SIMPLIFIED, tool-neutral:
                          NO SCAN (functional/sequential)     FULL SCAN
  Reach a target state    justify through MANY clock cycles   LOAD directly via shift chain (1 shift sequence)
  Observe internal node   propagate through MANY cycles       CAPTURE once, SHIFT out directly
  ATPG problem            sequential (exponential in depth)   COMBINATIONAL (one cycle) -> tractable
  Typical coverage        LOW (sequential wall)               HIGH (target, e.g. ~95-99%+ stuck-at, repr.)
  Cost                    none extra                          mux/flop (area), mux delay (timing), scan pins, power
# Same fault list (Ch2). Scan changes ACCESS, which changes the ATPG problem class -- that is the whole win.

7. Industry Flow — scan is the enabler for the whole structural flow

Scan sits between fault modeling and everything that consumes coverage:

8. Debugging Session — coverage capped no matter how many patterns

9. Common Mistakes

• Fighting low coverage with more functional patterns. The sequential wall is fundamental — you need scan (access).
• Blaming ATPG/tool for deep-state faults. They're unreachable without scan, not tool failures.
• Assuming scan is 'free.' It costs area, a functional-path mux delay, pins, and test power — real budgets.
• Choosing partial scan by default. It leaves sequential depth → lower, harder coverage; full scan is the norm.
• Ignoring scan-friendly RTL. Non-synchronous tricks break scan and re-create untestable state (Chapter 4).

10. Industry Best Practices

• Adopt full scan up front — it's a methodology decision, not a late patch.
• Budget the mux delay in functional timing and the scan area/pins early.
• Write scan-friendly RTL — synchronous design, controllable clocks/resets (Chapter 4).
• Plan shift-power management — many flops toggle during shift.
• Treat scan as the enabler — coverage, ATPG, compression all assume it (Chapters 4–7).

11. Senior Engineer Thinking

• Beginner: "Coverage is low — write more patterns and raise ATPG effort."
• Senior: "Without scan, reaching deep state is an exponential multi-cycle search — no pattern count fixes that. Full scan makes every flop loadable and readable, collapsing the problem to combinational — that's what lifts coverage. I pay the mux/area/pin/power cost because the coverage (and DPPM) gain is transformative."

The senior sees a coverage ceiling as an access/methodology problem and reaches for scan, not patterns.

12. Silicon Impact

Scan is the single most important enabling technology in manufacturing test — it's the reason high fault coverage is achievable at all on real, state-heavy designs. The deep contribution is a change in problem class: without scan, ATPG faces an exponential sequential search (justify state and propagate faults across many clock cycles) that is intractable and caps coverage near the floor; full scan gives direct controllability and observability of all state, collapsing the job to a tractable combinational problem solved one capture at a time. That collapse is what makes Chapters 5–7 (ATPG, coverage closure, compression) possible — they all assume scan. The costs are real and must be engineered: a mux per flop (area), a mux delay in the functional path (timing), scan pins (later relieved by compression, Ch7), and test power from mass flop toggling during shift. But the trade is overwhelmingly favorable — transformative coverage for a few percent of area — which is precisely why full scan is the default methodology across the industry, and why treating coverage shortfalls as 'pattern problems' rather than 'access problems' is a beginner's error. For the RTL/DV engineer, the implication is direct: your flops become scan cells, so scan-friendly, synchronous design and an awareness of the mux timing cost are part of doing your job well — and they're what let the fault models of Chapter 2 actually protect the customer through the DPPM commitment (1.5).

13. Engineering Checklist

• Committed to full scan as the methodology up front.
• Budgeted area (mux/flop), functional-path mux delay, scan pins, and test power.
• Confirmed the design is scan-friendly (synchronous, controllable clocks/resets — Ch4).
• Framed coverage as an access problem (scan), not a pattern-count problem.
• Verified scan enables combinational ATPG (flops as pseudo-PIs/POs) for the coverage target.

14. Try Yourself

1. Take a small state machine and argue why reaching a deep state functionally needs many precise clock cycles.
2. Estimate how the number of required input sequences grows with sequential depth (intuition for 'exponential').
3. Now add scan conceptually: show you can load the deep state directly and read it directly in a bounded number of shift cycles.
4. Explain how the ATPG problem becomes combinational (flops as pseudo-PIs/POs).
5. List scan's costs (mux area, path delay, pins, power) and argue why the coverage gain justifies them.

The reasoning is tool-neutral — pen and paper suffice. Real scan insertion/coverage come from Chapters 4–6. No paid tool required.

15. Interview Perspective

• Weak: "Scan lets you shift data in and out of flip-flops to test them."
• Good: "Scan makes flops controllable and observable by chaining them into a shift register, so you can load and read state."
• Senior: "Scan exists because embedded flops are uncontrollable and unobservable, so their faults are untestable. By chaining flops into a shift register, scan makes every flop directly loadable (controllability) and readable (observability) — and that collapses the sequential test problem into a combinational one: instead of an exponential multi-cycle search to justify and propagate through state, ATPG loads state directly, captures once, and reads it out, solving only the combinational logic between flops with flops as pseudo-PIs/POs. It costs a mux per flop (area + a functional-path delay), scan pins, and test power — but the coverage gain is transformative, so full scan is the industry default and the foundation of ATPG, coverage closure, and compression."

16. Interview / Review Questions

17. Key Takeaways

• Scan makes every flip-flop directly controllable (load any state) and observable (read any state) by chaining flops into a shift register driven from a few pins.
• That access collapses the intractable sequential test problem into a tractable combinational one — ATPG loads state, captures once, reads it out, solving only the combinational logic between flops (flops as pseudo-PIs/POs).
• Without scan, embedded state needs an exponential multi-cycle justify/propagate search → a coverage ceiling that more patterns/effort can't break — it's an access problem, not a pattern problem.
• Scan's honest costs — a mux per flop (area + functional-path delay), scan pins, test power — are real budget items, later relieved for pins by compression (Ch7).
• The coverage gain is transformative, so full scan is the industry default and the foundation of scan insertion, ATPG, coverage closure, and compression (Chapters 4–7). Next: 3.2 — the scan flip-flop (mux-D), scan's building block.

18. Quick Revision

Why scan exists (Ch3 opener). Embedded flops are uncontrollable (D upstream) + unobservable (Q downstream) → faults untestable (2.6). SCAN chains flops into a shift register → every flop directly loadable (controllability) + readable (observability). This collapses SEQUENTIAL test (exponential multi-cycle justify/propagate) into COMBINATIONAL test (load state → capture once → read out; flops = pseudo-PIs/POs) → tractable, high coverage. Costs: mux/flop (area + functional-path delay), scan pins, test power. Coverage gain is transformative → FULL SCAN is the default, the foundation for ATPG/coverage/compression. A coverage ceiling = an ACCESS problem, not a pattern problem. Next: 3.2 — the mux-D scan flip-flop.