Shift vs Capture Modes

Chapter 3 · Section 3.4 · Scan Architecture

Project thread — 3.3 ran the cycle; here we examine the shift vs capture modes and scan-enable timing that make it work — refined on the counter in 3.6.

1. Why Should I Learn This?

The mode switch (SE) and its timing are where scan meets real clocking — and where at-speed tests most often break.

• Shift mode (SE=1): slow shift clock, flops are a shift register, logic outputs don't-care → time + power live here.
• Capture mode (SE=0): functional/at-speed clock, logic exercised and captured → detection happens here.
• Scan-enable is a global signal that must settle at every flop before the capture edge — acute at-speed.
• X (unknown) captures corrupt the signature → X-masking (Ch7).

2. Real Silicon Story — the at-speed test that failed intermittently

A design passed stuck-at (slow capture) cleanly but failed at-speed transition patterns intermittently — some dies, some runs, no consistent fault. It looked like a flaky tester or a marginal design.

The real cause was scan-enable timing. At-speed capture used a fast, rated-clock capture edge, but SE was a slow, heavily-loaded global signal that hadn't fully settled to 0 across every flop by that fast edge. On some flops, SE was still effectively 1 at capture — so those flops were still in shift mode and captured scan data instead of the functional response, corrupting the result non-deterministically (depending on SE's exact arrival).

The fix was SE timing engineering — balance/pipeline SE, use a dedicated fast scan-enable, and ensure SE settles before the at-speed capture — not touching the patterns. Lesson: the mode switch is a timing-critical event; SE must reach every flop before capture, and this is hardest at-speed, where a fast capture races a slow global SE.

3. Factory Perspective — the two modes through each lens

• What the test engineer sees: the tester timing program — SE high through shift at the shift clock, SE low for a capture at the functional/at-speed clock — and the SE-settle-before-capture constraint.
• What the yield engineer sees: intermittent at-speed fails that trace to SE/clock timing, not defects — a test-setup issue to rule out before blaming silicon.
• What the RTL/DV engineer sees: that SE is a global control needing clean synchronous handling, and that uninitialized logic producing X at capture corrupts results (X-masking, Ch7).
• What management cares about: that shift is where test time and power go (1.4) and that at-speed SE timing is a schedule risk if not designed early — both feeding cost and DPPM (1.5).

4. Concept — the two modes, SE timing, and X

Shift mode (SE = 1):

• Flops = shift register; slow shift clock (tester-driven); data marches head → tail.
• Combinational logic outputs are don't-care — shift only moves scan data.
• Dominates test time (chain length × patterns, 1.4) and peaks scan power (mass toggling every cycle).

Capture mode (SE = 0):

• Flops act functionally; one (or a few) functional-clock pulses.
• Combinational logic between flops is exercised and its response captured — where detection happens.
• Stuck-at: slow capture. Transition/at-speed (2.3): rated-speed launch+capture, usually via OCC.

Scan-enable is a global, timing-critical control:

• SE switches the whole design between modes, so it fans out to every flop — a high-fanout global signal.
• Requirement: SE must settle to its capture value (0) at every flop before the capture edge. If SE is slow/skewed and some flops still see SE=1 at capture, they stay in shift mode and capture the wrong thing → corruption.
• Benign slow, dangerous fast: at slow capture SE has time to settle; at-speed the fast capture edge races the slow global SE → the classic failure (the story).
• Fixes: balance/pipeline SE, dedicated fast scan-enable, hold shift long enough, or OCC-coordinated capture.

Shift clock vs capture clock:

• Shift clock: slow, from the tester, used only to move scan data.
• Capture clock: the functional/at-speed clock (often on-chip, OCC) used for the one capture — the mode switch is really a clock + SE coordination.

X (unknown) values (light — full in Ch7):

• Captured X (from uninitialized or non-scan logic, bus contention) then shifted out corrupts the signature/compare → motivates X-handling / X-masking (Chapter 7).

The mode select routes either the scan path or the functional path into each flop:

5. Mental Model — a factory line in 'load' vs 'run' mode

Picture a production line with a master mode switch (SE).

• Load mode (shift, SE=1): the line runs slowly just to feed parts into every station (load scan data). What the machines would produce is irrelevant right now — you're only positioning material. This slow loading is most of the day (test time) and runs every motor (power).
• Run mode (capture, SE=0): you flip the switch, hit the machines once at full speed, and record what they produced — the actual test.
• The catch: the mode switch (SE) is one lever wired to every station, and it takes time to reach them all. If you hit run before the lever has fully flipped at every station, some stations are still in load mode and record garbage. At full speed (at-speed), the run pulse can beat the slow lever — so you must guarantee the lever has flipped everywhere first.

Load slowly, run once at speed — but make sure the mode lever has reached every station before you hit run.

6. Working Example — a mode timeline and an SE-not-settled failure

Walk the modes on the counter chain, then break it with bad SE timing:

# Mode timeline on a scan chain — REPRESENTATIVE, SIMPLIFIED, tool-neutral:
  SHIFT   (SE=1): slow shift clock x N -> load stimulus ; logic outputs DON'T-CARE ; scan power high
  (SE 1->0): scan-enable must SETTLE to 0 at EVERY flop  <-- the critical window
  CAPTURE (SE=0): one functional clock (stuck-at: slow ; transition: AT-SPEED via OCC) -> logic responds, captured
  SHIFT   (SE=1): slow shift clock x N -> unload response (+ load next) -> compare to golden

# SE-not-settled failure (at-speed) — REPRESENTATIVE:
  Capture clock = rated speed (fast). SE = global, heavily loaded, SLOW to fall.
  At the fast capture edge, SE is still ~1 at some far flops -> those flops CAPTURE SCAN DATA (still shifting)
  -> response corrupted on those bits -> INTERMITTENT at-speed fails (depend on exact SE arrival) -> false fails/escapes
  FIX: balance/pipeline SE, dedicated FAST scan-enable, or hold shift longer so SE settles BEFORE capture. NOT a pattern fix.

7. Industry Flow — mode/clock control across the cycle

The modes are a coordinated SE + clock sequence the flow must build and time:

8. Debugging Session — intermittent at-speed capture corruption

9. Common Mistakes

• Ignoring SE as a timing-critical global. It must settle at every flop before capture — especially at-speed.
• Assuming slow-capture success means at-speed is fine. At-speed races the slow SE — a new failure mode.
• Treating intermittent at-speed fails as tester flakiness. Usually SE-not-settled, a real design/timing issue.
• Forgetting logic is don't-care in shift. Only scan data matters during shift; the logic response is meaningless then.
• Overlooking X capture. Captured X (uninitialized/non-scan) corrupts the signature → plan X-masking (Ch7).

10. Industry Best Practices

• Treat scan-enable as a timing-critical net — balance/pipeline it, control skew (Chapter 4 CTS).
• Verify SE settles before capture, with margin, especially at-speed (OCC-coordinated).
• Separate shift clock (slow) from capture clock (functional/at-speed) cleanly in the program.
• Budget shift for time and power — shift dominates both (1.4).
• Plan X-handling so captured unknowns don't corrupt the response (Chapter 7).

11. Senior Engineer Thinking

• Beginner: "At-speed fails randomly — the tester is flaky."
• Senior: "Slow passes, at-speed fails intermittently — classic SE-not-settled. SE is a global signal, and the fast capture can beat it to the far flops, leaving them in shift mode during capture. I balance/pipeline SE, add a dedicated fast SE, and make capture wait until SE is settled — a timing fix, not a pattern fix."

The senior recognizes intermittent at-speed corruption as scan-enable timing and fixes SE distribution, not patterns.

12. Silicon Impact

Shift vs capture is where scan's logical elegance meets clocking reality, and mishandling it produces some of the most confusing, expensive test bugs. The division of labor is clean: shift mode does the slow, power-hungry, time-dominating work of loading and unloading state (logic don't-care), while capture mode is the single, decisive cycle where the logic under test responds and faults are detected — slow for stuck-at, at-speed for transition (2.3). The load-bearing subtlety is that scan-enable is a global control: it must settle at every flop before the capture edge, and while that's trivial at slow speed, it becomes a genuine race at-speed, where a fast capture clock can arrive before a slow, heavily-loaded SE has fallen everywhere — producing intermittent, data- and die-dependent capture corruption that is routinely (and wrongly) blamed on a flaky tester. The correct fix is SE timing engineering (balance/pipeline SE, dedicated fast SE, OCC coordination), a physical-design/DFT task, not a pattern edit — and getting it right is a real schedule risk if left late. Two more impacts land on cost and quality: shift is where test time and power live (motivating compression, Ch7, and shift-power care), and captured X values corrupt the response unless handled (X-masking, Ch7). For the RTL/DV and physical engineer, the message is that the global scan-enable deserves first-class timing treatment, because the validity of the capture — the moment that actually detects defects and underwrites the DPPM commitment (1.5) — depends on it.

13. Engineering Checklist

• Treated scan-enable as a timing-critical global (balanced/pipelined, skew-controlled).
• Verified SE settles to capture value at every flop before the capture edge — with at-speed margin.
• Separated slow shift clock from functional/at-speed capture clock (OCC) in the program.
• Budgeted shift time and shift power (dominant — 1.4).
• Planned X-handling so captured unknowns don't corrupt the response (Ch7).

14. Try Yourself

1. Draw a timeline: SE=1 with a slow shift clock (N cycles), then SE=0 with one functional capture clock.
2. Mark the SE settle window — the time SE must reach 0 at all flops before capture.
3. Show an at-speed case where a fast capture edge arrives before SE settles at a far flop → that flop captures scan data (corruption).
4. List three fixes (balance/pipeline SE, dedicated fast SE, hold shift) that resolve it without changing patterns.
5. Explain why the logic outputs are don't-care during shift, and where shift power/time come from.

The timing reasoning is tool-neutral. Real SE distribution/OCC come from physical design + Chapter 4; at-speed patterns from Chapter 5. No paid tool required.

15. Interview Perspective

• Weak: "Shift mode moves data, capture mode captures results."
• Good: "Scan-enable picks shift (SE=1, shift register, slow clock) or capture (SE=0, one functional clock where the logic is tested)."
• Senior: "SE selects two modes. Shift (SE=1): a slow shift clock marches scan data head-to-tail; the logic outputs are don't-care; this is where test time and power go. Capture (SE=0): one functional (or at-speed, via OCC) clock exercises the logic between flops and captures the response — where detection happens. The critical part is that scan-enable is a global signal that must settle at every flop before the capture edge; that's easy slow but a race at-speed, where a fast capture can beat a slow SE and leave some flops still shifting — capturing scan data and corrupting results intermittently. The fix is SE timing (balance/pipeline, dedicated fast SE), not the patterns. And captured X values must be masked so they don't corrupt the signature."

16. Interview / Review Questions

17. Key Takeaways

• A scan chain runs in two modes, both selected by scan-enable (SE): shift (SE=1) and capture (SE=0).
• Shift mode: a slow shift clock makes the flops a shift register to load/unload scan data; the combinational logic outputs are don't-care — and this is where test time (1.4) and scan power are spent.
• Capture mode: one (or a few) functional-clock pulses exercise the logic between flops and capture the response — where fault detection happens; stuck-at uses a slow capture, transition/at-speed (2.3) a rated-speed capture via OCC.
• Scan-enable is a global signal that must settle to its capture value at every flop before the capture edge — trivial at slow speed but a race at-speed, causing intermittent capture corruption if SE arrives late; the fix is SE timing (balance/pipeline/dedicated SE), not patterns.
• Captured X (unknown) values corrupt the response/signature → plan X-handling / X-masking (Chapter 7). Next: 3.5 — chain count, length & balancing.

18. Quick Revision

Shift vs capture modes. SE selects both. SHIFT (SE=1): slow shift clock, flops = shift register, load/unload scan data, logic outputs don't-care → where test time + power go (1.4). CAPTURE (SE=0): ONE functional (stuck-at) or at-speed (transition, via OCC) clock → logic exercised + response captured → where detection happens. SCAN-ENABLE is a GLOBAL signal → must settle to 0 at EVERY flop before the capture edge; easy slow, a race at-speed → late SE leaves flops in shift mode → intermittent capture corruption → fix SE timing (balance/pipeline/dedicated fast SE), NOT patterns. Captured X corrupts signature → X-masking (Ch7). Next: 3.5 — chain count, length & balancing.