DFT · Chapter 10 · Boundary Scan & JTAG
Why Boundary Scan Exists
Once chips are soldered onto a board, the interconnects between them, meaning solder joints and board traces, can be open, shorted, or wrong, but the pins can no longer be physically probed. Dense surface-mount boards and ball-grid-array packages that hide their pins underneath made the old bed-of-nails probing infeasible. Boundary scan, standardized as IEEE 1149.1 and universally called JTAG, solves this by placing a boundary-scan cell at every chip pin, chaining those cells into a register accessible through a standard four- or five-wire serial test access port. Now a tester can control and observe every pin from the serial port, driving a value out one chip's pin and observing it at another across the interconnect, so opens and shorts are tested without any physical probe. The same serial access also became the universal doorway to on-chip features like starting BIST, in-system programming, and debug.
Foundation12 min readDFTBoundary ScanJTAGIEEE 1149.1Board Test
Chapter 10 · Section 10.1 · Boundary Scan & JTAG
Project thread — the mini-SoC (scan/ATPG + MBIST + LBIST) goes onto a board; JTAG tests its interconnect and provides access to start its BIST (9.5). 10.6 traces a path end-to-end.
1. Why Should I Learn This?
Boundary scan is how boards are tested and how chips are accessed in-system — the standard behind interconnect test, BIST access, ISP, and debug.
- Problem: soldered boards can't be physically probed (dense surface-mount, hidden BGA pins).
- Solution: a boundary-scan cell at every pin, chained, accessible via a 4-wire serial TAP (TCK/TMS/TDI/TDO).
- Control + observe every pin from the serial port → test board interconnect (opens/shorts) without probes.
- Bonus (9.5 bridge): the same access starts BIST, reads signatures, does ISP and debug — IEEE 1149.1.
2. Real Silicon Story — the BGA board you couldn't probe
A team moved to a dense board with BGA packages — the pins are balls underneath the package, with no exposed leads. Their existing board test used a bed-of-nails fixture: physical probes touching every net. On the new board, most nets were inaccessible — hidden under the BGAs — so the fixture couldn't reach them, and solder defects (opens under the balls, shorts between adjacent traces) were escaping to the field.
You cannot physically probe what's under a BGA. The board-test problem had become structurally unsolvable with probes.
The fix was boundary scan (IEEE 1149.1): with a boundary-scan cell at every chip pin and a serial TAP, the tester could drive one chip's pin and observe another chip's pin electronically, over 4 wires — testing the hidden interconnect with no physical access. As a bonus, the same TAP let them start the chips' BIST and program them in-system. Lesson: dense/hidden-pin boards killed physical probing, and boundary scan replaced the probe with an electronic one at every pin — the only way to test modern board interconnect (and the universal in-system access mechanism).
3. Factory Perspective — boundary scan through each lens
- What the board-test engineer sees: a serial JTAG interface that controls/observes every pin — interconnect test (opens/shorts) with no bed-of-nails, on hidden-pin boards.
- What the yield engineer sees: solder/interconnect defects (a huge share of board failures) now detectable — fewer board-level escapes.
- What the DFT/RTL engineer sees: that the chip must be 1149.1-compliant (boundary cells + TAP), and that the same access provides the BIST/debug doorway (9.5) — an integration requirement.
- What the system engineer sees: JTAG as the universal access — in-system BIST, flash programming (ISP), and debug — all over the same 4 wires.
4. Concept — the board-test problem and the boundary-scan solution
The problem — you can't probe soldered, dense, hidden-pin boards:
- Chips are good (Chapters 1–9), but the board interconnect (solder joints, traces) can be open/short/wrong.
- Classic bed-of-nails test needs a physical probe on every net — but dense surface-mount and BGA (pins under the package) leave nothing to touch → probing is infeasible.
The solution — boundary scan (IEEE 1149.1 / JTAG):
- Put a boundary-scan cell at every chip I/O pin — a cell that can capture the pin's value and/or drive a value onto the pin, under test control (10.3).
- Chain all the cells into a boundary-scan register (a shift register around the chip's periphery — its 'boundary').
- Make it accessible via a standard serial TAP: TCK (test clock), TMS (mode select), TDI (data in), TDO (data out) — and optional TRST (reset) — driven by the TAP controller (10.2).
What that buys — an electronic probe at every pin:
- Control any output pin (drive a value) and observe any input pin (capture a value) from the serial port.
- Interconnect test: drive a value out chip A's output pin, observe it at chip B's input pin — if it doesn't arrive → an open; if two nets read the same → a short. No physical probe needed (10.4/10.6).
The bonus — universal in-system access (the 9.5 bridge):
- The same TAP reaches on-chip data registers, so JTAG is the standard way to: start BIST and read the signature (LBIST/MBIST, Chapters 8–9), program flash/CPLD (ISP), and debug.
- This is why JTAG became the universal test/debug/programming access — far beyond its original board-test purpose.
A crucial scope note:
- Boundary scan tests the board interconnect (between chips), not the chip's internal logic — that's scan/ATPG (Chapters 3–7). They're complementary: scan/ATPG for inside the chip; boundary scan for between the chips.
5. Mental Model — inspecting sealed plumbing from a control panel
Boundary scan is like inspecting a building's plumbing after the walls are sealed, using valves and sensors at every junction wired to a single control panel.
- Once the walls are closed (the board is soldered, BGA pins hidden), you can't physically reach the pipes (can't probe the pins) — a plumber with a wrench (a bed-of-nails probe) is useless.
- So the builder installed a valve and a sensor at every pipe junction (a boundary-scan cell at every pin), all wired to a control panel (the serial TAP).
- Now, from the panel, you can open a valve to send water down one pipe (drive a pin) and read a sensor at the far junction (observe a pin) — if the water doesn't arrive, there's a blockage (an open); if it shows up in the wrong pipe, there's a cross-connection (a short). No wall needs opening.
- The same panel also lets you run the building's self-diagnostics (start BIST), update firmware (ISP), and watch operations (debug) — one panel, many jobs.
Seal the walls, but wire a valve+sensor to every junction and a control panel — that's boundary scan: inspect the hidden interconnect (and access everything) from a few wires.
6. Working Example — interconnect test without a probe
Test a board net between two chips via boundary scan:
# Board interconnect test via boundary scan - REPRESENTATIVE, SIMPLIFIED, tool-neutral:
Board: Chip A output pin PA --- (net) --- Chip B input pin PB (interconnect to test for OPEN/SHORT)
WITHOUT a probe (BGA pins hidden), use the serial TAP (TCK/TMS/TDI/TDO):
1) Load an interconnect-test instruction (EXTEST, 10.4) into A and B via the TAP
2) DRIVE a 1 from A's boundary cell onto PA -> the net
3) CAPTURE the net at B's boundary cell (PB)
4) SHIFT B's captured value out on TDO and compare:
A drove 1, B captured 1 -> net OK
A drove 1, B captured 0 -> OPEN (or short to ground) -> DEFECT (no physical probe needed!)
two nets both capture the same wrong value -> SHORT between them
# Boundary scan = an ELECTRONIC probe at every pin -> test the board INTERCONNECT with no bed-of-nails.
# (Chip INTERNALS are tested by scan/ATPG, Ch3-7 -- boundary scan tests BETWEEN the chips.)# The 9.5 bridge - JTAG as BIST/ISP/debug ACCESS - REPRESENTATIVE:
The same TAP reaches on-chip DATA REGISTERS -> a USER instruction can:
START LBIST/MBIST and READ the signature/result (in-system self-test access, 9.5)
PROGRAM flash/CPLD (in-system programming, ISP)
DEBUG (many SoC debug ports are JTAG)
# JTAG = the UNIVERSAL test/debug/programming access standard (IEEE 1149.1).7. Industry Flow — boundary scan tests the board, not the chip internals
Boundary scan complements chip-level test, covering the board interconnect and access:
8. Debugging Session — a hidden-pin board escapes interconnect defects
A dense board with BGA packages escapes interconnect defects (solder opens/shorts) because bed-of-nails probing can't reach the pins hidden under the packages; the fix is boundary scan (IEEE 1149.1) which puts an electronically controllable/observable cell at every pin reached via a serial TAP, so the interconnect is tested without physical probes -- and the same access starts on-chip BIST
HIDDEN-PIN BOARDS CAN'T BE PROBED — BOUNDARY SCAN IS THE ELECTRONIC PROBEA dense board with BGA packages is escaping interconnect defects — solder opens under the balls, shorts between adjacent traces — into the field. The bed-of-nails fixture can't reach the nets hidden under the packages.
The board's interconnect must be tested, but the pins are physically inaccessible — hidden under BGA packages and dense surface-mount — so a bed-of-nails fixture, which needs a physical probe on every net, structurally cannot reach them. Board test has always relied on touching the nets: a fixture with spring-loaded probes contacts every node, drives values, and measures — detecting opens (a net that doesn't connect), shorts (nets wrongly connected), and missing/wrong parts. That approach depends on physical access, and modern packaging removed it: BGA packages put the pins as solder balls underneath the package (no exposed leads to touch), and dense surface-mount leaves no room for probe points on many nets. So a growing fraction of the interconnect is un-probeable, and its defects — a real and common board failure mode — escape because there is literally nowhere to put a probe. This is not a test-program weakness; it's a physical-access wall that probing cannot cross, and it gets worse with every increase in density and pin count.
Adopt boundary scan (IEEE 1149.1) — put an electronically controllable/observable cell at every chip pin, reached via a serial TAP — so the interconnect is tested without any physical probe. Make each chip 1149.1-compliant: a boundary-scan cell at every I/O pin (10.3), chained into a boundary-scan register, driven by a TAP (TCK/TMS/TDI/TDO, 10.2). Then the tester drives a value out one chip's output pin and observes it at the connected chip's input pin electronically (via EXTEST, 10.4/10.6): a value that doesn't arrive is an open; two nets reading the same is a short — all without touching the board. Daisy-chain the chips' TAPs into one board JTAG chain (10.5) so the whole board's interconnect is testable over a few wires, and use BYPASS to skip non-targeted chips. As a bonus, the same TAP provides access to start on-chip BIST and read results (the 9.5 bridge), program devices (ISP), and debug. The principle to lock in: modern boards are soldered, dense, and use hidden-pin packages (BGA), so their interconnects can no longer be physically probed by a bed-of-nails fixture — boundary scan (IEEE 1149.1 / JTAG) solves this by placing a controllable/observable boundary-scan cell at every chip pin, chained into a boundary-scan register accessible over a standard four-wire serial TAP, which replaces the physical probe with an electronic one at every pin so the board interconnect (opens/shorts/solder defects) can be tested without physical access; and the same serial access is the universal in-system doorway to BIST, programming, and debug — so boundary scan tests between the chips while scan/ATPG tests inside them. (The TAP controller is 10.2; boundary cells 10.3; instructions like EXTEST/BYPASS 10.4; board/in-system use 10.5; a worked path 10.6.)
9. Common Mistakes
- Assuming chip test covers board defects. Scan/ATPG tests inside the chip — interconnect needs boundary scan.
- Relying on bed-of-nails for dense/BGA boards. Hidden pins are un-probeable — use boundary scan.
- Thinking boundary scan tests chip internals. It tests between the chips (interconnect) — complementary to scan/ATPG.
- Skipping 1149.1 compliance. Without boundary cells + a TAP, the board isn't testable and there's no in-system access.
- Ignoring the access bonus. JTAG is also the BIST/ISP/debug doorway (9.5) — not just interconnect test.
10. Industry Best Practices
- Make every chip IEEE 1149.1-compliant — boundary cells + TAP — for board testability and access.
- Use boundary scan for interconnect (opens/shorts/solder) on dense/hidden-pin boards — no bed-of-nails.
- Provide a BSDL file per chip (10.3) so board test knows the boundary scan.
- Leverage the TAP for access — in-system BIST (9.5), ISP, debug.
- Keep scan/ATPG (chip internals) and boundary scan (interconnect) as complementary layers.
11. Senior Engineer Thinking
- Beginner: "We have great chip test — the board is covered."
- Senior: "Chip test (scan/ATPG/BIST) covers inside the chips — but the board interconnect (solder opens/shorts) is a different defect class, and on a BGA board you can't physically probe it. I make the chips 1149.1-compliant and test the interconnect with boundary scan — an electronic probe at every pin over a 4-wire TAP — no bed-of-nails. And that same TAP gives me in-system BIST/ISP/debug access."
The senior tests the board interconnect with boundary scan (not chip test) and uses the TAP as universal access.
12. Silicon Impact
Boundary scan exists because the board became un-probeable — and yet its interconnect must still be tested. As packaging moved to dense surface-mount and BGA (pins hidden under the package), the decades-old bed-of-nails approach — a physical probe on every net — ran out of nets to touch, so a large and growing share of board interconnect defects (solder opens, shorts, missing/mis-placed parts — among the most common board failures) had no way to be caught. IEEE 1149.1 (JTAG) solved this with a structural idea as elegant as scan itself: put a controllable/observable cell at every chip pin, chain them, and expose them over a standard 4-wire serial TAP — replacing the physical probe with an electronic one at every pin. That makes the hidden interconnect testable (drive one chip's pin, observe the connected chip's pin, detect opens/shorts) with no physical access, which is the only way to test modern boards. The scope discipline matters: boundary scan tests between the chips (interconnect); scan/ATPG tests inside the chips — complementary layers, not substitutes. And the second-order impact is arguably even larger: because the same serial TAP reaches on-chip data registers, JTAG became the universal in-system access mechanism — the standard way to start BIST and read its signature (the direct 9.5 bridge — this is how the in-field self-test of Chapters 8–9 is triggered and read), to program flash/CPLDs in-system (ISP), and to debug (most SoC debug ports are JTAG). For the DFT/system engineer, the takeaway is that 1149.1 compliance is a board-testability and access requirement on every chip, and boundary scan is the layer that makes dense, hidden-pin boards manufacturable, programmable, self-testable, and debuggable — the foundation the rest of Chapter 10 builds out: the TAP (10.2), the cells (10.3), the instructions (10.4), the board/in-system use (10.5), and a worked path (10.6).
13. Engineering Checklist
- Made each chip IEEE 1149.1-compliant (boundary cells + TAP) — board testability + access.
- Planned interconnect test (EXTEST) via boundary scan for dense/hidden-pin boards (no bed-of-nails).
- Provided a BSDL file per chip (10.3) for board test.
- Used the TAP for in-system access — BIST (9.5), ISP, debug.
- Kept scan/ATPG (internals) and boundary scan (interconnect) as complementary layers.
14. Try Yourself
- Explain why a BGA board can't be bed-of-nails probed.
- Sketch two chips + a net; add a boundary cell at each pin and a serial TAP — show driving/observing the net.
- Describe an interconnect test (drive A's output, observe B's input) that detects an open and a short — no probe.
- Distinguish boundary scan (between chips) from scan/ATPG (inside chips) — complementary.
- Name three access uses of the same TAP (start BIST, ISP, debug — the 9.5 bridge).
The concepts are tool-neutral; boundary scan is IEEE 1149.1. No paid tool required to reason about why it exists.
15. Interview Perspective
- Weak: "Boundary scan tests the chip through JTAG."
- Good: "Boundary-scan cells at the pins let you test the board interconnect via a serial port without probing."
- Senior: "Once chips are soldered onto a dense, BGA board, you can't physically probe the pins (they're hidden under the packages), but the interconnect — solder joints, traces — can be open or shorted and must be tested. Boundary scan (IEEE 1149.1 / JTAG) puts a controllable/observable cell at every chip pin, chains them into a boundary-scan register, and exposes it over a 4-wire serial TAP (TCK/TMS/TDI/TDO). So you drive one chip's output pin and observe the connected chip's input pin electronically — testing opens/shorts with no physical probe. It tests between the chips; scan/ATPG tests inside them — complementary. And the same TAP is the universal in-system access — start BIST and read the signature (the in-field self-test of Ch9), program flash (ISP), debug. That's why JTAG is everywhere."
16. Interview / Review Questions
17. Key Takeaways
- Once chips are soldered onto a board, the interconnects between them (solder joints, traces) can be open/shorted/wrong — a board-level defect class that must be tested.
- Dense surface-mount and BGA packaging hide the pins, making classic bed-of-nails physical probing infeasible — there's nothing to touch.
- Boundary scan (IEEE 1149.1 / JTAG) solves this: a controllable/observable cell at every chip pin, chained into a boundary-scan register, accessible over a standard 4-wire serial TAP (TCK/TMS/TDI/TDO) — an electronic probe at every pin.
- It tests the board interconnect (drive one chip's pin, observe the connected chip's pin → detect opens/shorts) without any physical probe — and it tests between the chips, complementing scan/ATPG (inside the chips).
- The same serial TAP is the universal in-system access — start BIST and read the signature (the 9.5 bridge), program in-system (ISP), and debug — which is why JTAG became the universal test/debug/programming standard. Next: 10.2 — the JTAG TAP controller.
18. Quick Revision
Why boundary scan exists (Ch10 opener). Soldered boards have INTERCONNECT (solder joints/traces) that can be open/short — but dense SMT + BGA HIDE the pins → bed-of-nails physical probing is infeasible (nothing to touch). BOUNDARY SCAN (IEEE 1149.1 / JTAG): a controllable/observable CELL at every chip pin, chained into a boundary-scan register, reached over a 4-wire serial TAP (TCK/TMS/TDI/TDO) → an ELECTRONIC probe at every pin → drive chip A's output pin, observe chip B's input pin → test interconnect (opens/shorts) with NO physical probe. Tests BETWEEN chips; scan/ATPG tests INSIDE them (complementary). Same TAP = universal in-system ACCESS: start BIST + read signature (9.5 bridge), ISP programming, debug. Next: 10.2 — the JTAG TAP controller.