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DFT · Chapter 10 · Boundary Scan & JTAG

JTAG Instructions (BYPASS, EXTEST, SAMPLE)

This lesson is the JTAG instruction set: what each instruction is and does. Every instruction shifted into the instruction register does two things at once. It selects which data register sits between the data-in and data-out pins, and it defines what operation the boundary cells perform. There are three mandatory instructions. BYPASS selects a single one-bit register so the chip is skipped, shortening the board chain when testing other chips. SAMPLE and PRELOAD take a non-intrusive snapshot of the pins and set up the boundary cells before external test. EXTEST drives the boundary cells onto the output pins and captures the input pins to test the board interconnect. Optional instructions include IDCODE for the device ID, and user instructions access on-chip BIST, in-system programming, and debug. Always preload before EXTEST.

Intermediate13 min readDFTJTAG InstructionsEXTESTBYPASSSAMPLE/PRELOAD

Chapter 10 · Section 10.4 · Boundary Scan & JTAG

Project thread — the mini-SoC uses EXTEST for board interconnect test and a USER instruction to access its BIST (9.5); 10.6 runs both.

1. Why Should I Learn This?

The instructions are what JTAG can do — each selects a register and an operation, from interconnect test to BIST access.

  • BYPASS (mandatory): 1-bit register → skip the chip (shorten the chain).
  • SAMPLE/PRELOAD (mandatory): snapshot the pins (observe) / set up the boundary cells before EXTEST.
  • EXTEST (mandatory): drive outputs + capture inputs → board interconnect test (opens/shorts).
  • IDCODE (common): read device ID; USER instructions: BIST/ISP/debug access (the 9.5 bridge).

2. Real Silicon Story — EXTEST without PRELOAD

A board-test program went straight to EXTEST to test the interconnect — and got erratic results: some nets read wrong, and there were signs of drive contention on the board. The team suspected defective boards or a flawed EXTEST.

The bug was sequence. EXTEST immediately drives the boundary cells' update flops onto the output pins — but those flops held whatever was there (from reset/capture), i.e. undefined/garbage values. So on entering EXTEST, the chips drove random values onto the board nets — including cases where two drivers fought (contention) or a net was driven to the wrong value before the intended test pattern was loaded. The interconnect test was meaningless because the starting drive state was undefined.

The fix is the mandatory PRELOAD: use SAMPLE/PRELOAD to load known, safe values into the boundary cells first, then enter EXTEST so the pins drive defined values. Lesson: PRELOAD the boundary cells to known values before EXTEST — that's exactly why SAMPLE/PRELOAD is mandatory — or EXTEST drives undefined values and the interconnect test is garbage.

3. Factory Perspective — instructions through each lens

  • What the board-test engineer sees: the instruction sequence — PRELOAD → EXTEST for interconnect, BYPASS to skip non-targeted chips, IDCODE to verify the right device — from the BSDL.
  • What the DFT engineer sees: the mandatory set (BYPASS/SAMPLE-PRELOAD/EXTEST) for 1149.1 compliance, plus user instructions for BIST/ISP/debug.
  • What the system engineer sees: the user instructions as the access doorway — start BIST, read the signature (9.5), program, debug.
  • What management cares about: that the chip's instruction set delivers board test and in-system access — the full 1149.1 value (10.1).

4. Concept — what each instruction selects and does

Every instruction: selects a data register + defines an operation.

BYPASS (mandatory):

  • Selects: a 1-bit bypass register between TDI/TDO.
  • Does: skips this chip — data passes through in 1 bit — so you can shorten the board chain when testing other chips (don't shift through this chip's long BSR).

SAMPLE/PRELOAD (mandatory):

  • Selects: the boundary-scan register (BSR).
  • SAMPLE: captures the pin values during normal operation — a non-intrusive snapshot (observe what the pins are doing) without disturbing function.
  • PRELOAD: loads values into the boundary cells (their update flops) to set them up — used to preload known/safe drive values before EXTEST.

EXTEST (mandatory) — the core board test:

  • Selects: the BSR.
  • Does: drives the boundary cells onto the output pins and captures the input pins → test the board interconnect between chips (drive A's output, capture B's input → opens/shorts, 10.6).
  • Requires PRELOAD first (known drive values) — else it drives undefined values (the story).

IDCODE (optional, common):

  • Selects: a (typically 32-bit) device-identification register.
  • Does: read the device ID (verify the right chip is present); auto-selected at Test-Logic-Reset if present.

INTEST (optional, now rare):

  • Drives the chip's internal logic from the boundary — largely superseded by scan/ATPG (Chapters 3–7) for internals.

USER / private instructions (the 9.5 bridge):

  • Select a user data register to access on-chip features: run BIST and read the LBIST/MBIST signature (in-system self-test access, 9.5), program flash/CPLD (ISP), and debug.
Each JTAG instruction selects a data register and operation: BYPASS skips the chip, SAMPLE/PRELOAD snapshots and sets up, EXTEST drives outputs and captures inputs, IDCODE reads the ID, USER accesses on-chip featuresBYPASS (mandatory)1-bit register → skip thechipSAMPLE/PRELOAD(mandatory)BSR: snapshot pins / set upcellsEXTEST (mandatory)BSR: drive outputs +capture inputs →interconnectIDCODE (common)read device-ID registerINTEST (rare)internal test (scan/ATPGsuperseded)USER (BIST/ISP/debug)user register → 9.5 accessbridge12
Figure 1 - JTAG instructions: each selects a data register + an operation (representative). Loading an instruction into the IR (10.2) SELECTS which DR is between TDI/TDO and what the boundary cells do. BYPASS -> 1-bit register (SKIP the chip). SAMPLE/PRELOAD -> BSR: SAMPLE snapshots the pins (observe, non-intrusive); PRELOAD sets up the boundary cells (before EXTEST). EXTEST -> BSR: DRIVE output pins + CAPTURE input pins (board interconnect test). IDCODE -> device-ID register (read ID). USER -> a user register (BIST/ISP/debug access, the 9.5 bridge). Mandatory: BYPASS, SAMPLE/PRELOAD, EXTEST.

5. Mental Model — mode buttons on a universal remote

JTAG instructions are like the mode buttons on a universal remote for the chip — each switches what the buttons control.

  • BYPASS = a 'pass-through' button — this device gets out of the way (a 1-bit hop) so you can reach the next device in the chain quickly.
  • SAMPLE = a 'freeze-frame' button — take a snapshot of what the pins are doing right now, without interrupting the show (non-intrusive observe).
  • PRELOAD = a 'set the stage' button — load the values you'll want the pins to drive, before you go live.
  • EXTEST = the 'broadcast' button — now the device actively drives its output pins (with the values you preloaded) and watches its input pins — the live board-interconnect test. You must set the stage (PRELOAD) before you broadcast (EXTEST), or you broadcast noise.
  • IDCODE = a 'who are you?' button — read the device's ID.
  • USER buttons = the special features — run diagnostics (BIST), update firmware (ISP), watch internals (debug).

Each instruction switches what the serial port controls — and you always 'set the stage' (PRELOAD) before you 'broadcast' (EXTEST).

6. Working Example — an interconnect test sequence

Trace the mandatory sequence for a board interconnect test:

Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
# Board interconnect test instruction sequence - REPRESENTATIVE, SIMPLIFIED, tool-neutral:
  (TAP navigation per 10.2: reset -> Shift-IR to load instruction -> Shift-DR to shift the register)
  1) On the TARGET chips (A and B): load SAMPLE/PRELOAD, then PRELOAD the boundary cells to KNOWN/safe drive values
     (e.g. set A's output cell for net X to 1) -- so nothing drives garbage.
  2) On NON-target chips: load BYPASS -> 1-bit -> skip them (shorten the chain).
  3) On A and B: load EXTEST -> A DRIVES its output pins (net X = 1), B CAPTURES its input pins (net X)
  4) Shift the BSR out on TDO and COMPARE:
     B captured 1 -> net X OK ; B captured 0 -> OPEN (or short to gnd) ; two nets same wrong value -> SHORT
  (Optional: load IDCODE first to verify the right devices are present.)
# WRONG: EXTEST WITHOUT PRELOAD -> output cells drive UNDEFINED values -> contention/mis-drive -> garbage results.
Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
# The 9.5 bridge - a USER instruction for BIST access - REPRESENTATIVE:
  Load a USER instruction -> selects a USER data register connected to the on-chip BIST controller
  -> write 'start LBIST/MBIST' + read back the SIGNATURE / go-nogo via TDO (in-system self-test access, 9.5)
  Other USER instructions: program flash (ISP), debug. -> JTAG = universal in-system access.

7. Industry Flow — the interconnect-test instruction flow

The mandatory instructions sequence a board interconnect test:

Optionally IDCODE, then PRELOAD known values, BYPASS non-targets, EXTEST to drive and capture, shift out and compare for opens/shortsInterconnect test: (IDCODE) → PRELOAD → BYPASS others → EXTEST → compareInterconnect test: (IDCODE) → PRELOAD → BYPASS others → EXTEST → compare1IDCODE (optional)verify the right devices2PRELOAD (SAMPLE/PRELOAD)known drive values — before EXTEST3BYPASS non-targets1-bit → shorten the chain4EXTESTdrive outputs + capture inputs5Shift BSR out → compareopen/short (or USER → BIST, 9.5)
Figure 2 - the interconnect-test instruction flow (representative). Optionally IDCODE to verify devices. On target chips: SAMPLE/PRELOAD to PRELOAD the boundary cells to known drive values (mandatory before EXTEST). On non-target chips: BYPASS (1-bit) to shorten the chain. On targets: EXTEST -> drive output pins + capture input pins -> shift the BSR out -> COMPARE (open/short). A USER instruction can instead access on-chip BIST (start + read signature, 9.5). Rule: PRELOAD before EXTEST, or outputs drive undefined values.

8. Debugging Session — EXTEST drives garbage (no PRELOAD)

1

An EXTEST interconnect test gives erratic results with signs of drive contention, and the team suspects bad boards; EXTEST was entered without PRELOAD first, so the boundary cells' update flops held undefined values and drove garbage onto the board nets -- the fix is the mandatory SAMPLE/PRELOAD to load known, safe drive values into the boundary cells before EXTEST

PRELOAD THE BOUNDARY CELLS TO KNOWN VALUES BEFORE EXTEST — OR OUTPUTS DRIVE GARBAGE
Symptom

An EXTEST interconnect test gives erratic results — some nets read wrong, and there are signs of drive contention on the board. The team suspects defective boards or a broken EXTEST.

Root Cause

EXTEST was entered without first PRELOADing the boundary cells, so the cells' update flops held undefined values and drove garbage onto the board nets the moment EXTEST took effect — including cases where two drivers fought (contention). EXTEST's job is to drive the boundary cells' update-flop values onto the output pins and capture the input pins — a live operation on the board. But EXTEST drives whatever the update flops currently hold; it does not magically start from a known state. If you enter EXTEST without having PRELOADed the boundary cells, those flops hold leftover/undefined values (from reset or a prior capture), so on entering EXTEST the chips drive random values onto the nets — a net meant to be driven to 1 by chip A might be driven to 0, or two chips might drive the same net to opposite values (contention). The interconnect measurements are therefore meaningless, because the initial drive state was never defined — and it looks like bad boards or a flawed test, when in fact the test sequence was wrong. This is precisely the failure mode SAMPLE/PRELOAD is mandatory to prevent: PRELOAD exists so you can set up known, safe drive values before EXTEST goes live.

Fix

Use the mandatory SAMPLE/PRELOAD to load known, safe drive values into the boundary cells before entering EXTEST — then the interconnect test drives defined values and is meaningful. Sequence it correctly: load SAMPLE/PRELOAD, PRELOAD each boundary cell to its intended known drive value (the test pattern for the interconnect — and safe values on any net you're not actively driving, to avoid contention), then load EXTEST so the pins drive exactly those preloaded values, capture the inputs, shift the BSR out, and compare for opens/shorts. Verify with the BSDL that you're preloading the right cells for the right pins. (Also BYPASS the non-target chips so their pins aren't part of the active test unexpectedly.) The principle to lock in: a JTAG instruction (loaded into the IR) both selects a data register and defines the boundary-cell operation — BYPASS selects a 1-bit register to skip the chip, SAMPLE/PRELOAD selects the boundary-scan register to snapshot the pins (observe) or preload known drive values, EXTEST selects the boundary-scan register to drive the output pins and capture the input pins for interconnect test, IDCODE reads the device ID, and user instructions access on-chip BIST/ISP/debug — and because EXTEST drives whatever the boundary cells hold, you must PRELOAD known values before EXTEST (which is exactly why SAMPLE/PRELOAD is mandatory), or the outputs drive undefined values and the interconnect test is garbage. (The IR selection is 10.2; the boundary cells are 10.3; the board interconnect test in full is 10.5/10.6.)

9. Common Mistakes

  • EXTEST without PRELOAD. Output cells drive undefined values → contention/garbage — PRELOAD known values first.
  • Not BYPASSing non-target chips. Shift through their long BSR unnecessarily (or include them by accident) — BYPASS them.
  • Confusing EXTEST and INTEST. EXTEST = board interconnect (between chips); INTEST = internal (rare, use scan/ATPG).
  • Forgetting SAMPLE is non-intrusive. SAMPLE snapshots pins without disturbing function — good for observe.
  • Omitting mandatory instructions. BYPASS/SAMPLE-PRELOAD/EXTEST are required for 1149.1 compliance.

10. Industry Best Practices

  • Always PRELOAD before EXTEST (known/safe drive values) — mandatory for a valid interconnect test.
  • BYPASS non-target chips to shorten the board chain.
  • Use IDCODE to verify the right devices are present before testing.
  • Expose on-chip BIST/ISP/debug via user instructions — the in-system access (9.5).
  • Document the full instruction set in BSDL so tools can drive it.

11. Senior Engineer Thinking

  • Beginner: "EXTEST gives garbage — the boards must be bad."
  • Senior: "Did you PRELOAD first? EXTEST drives whatever the boundary cells hold — without PRELOAD, they drive undefined values → contention/garbage, not a board fault. I SAMPLE/PRELOAD known values, then EXTEST, BYPASS the non-targets, and compare. And for in-system self-test I use a user instruction to start BIST and read the signature (9.5)."

The senior PRELOADs before EXTEST and uses BYPASS/IDCODE/user instructions deliberately — sequence is everything.

12. Silicon Impact

The JTAG instruction set is what turns the TAP + boundary register (10.2/10.3) into actual capabilities — each instruction selects a register and an operation, and together they deliver the entire boundary-scan toolkit: interconnect test, chain management, device ID, and in-system access. The three mandatory instructions map to the essential jobs: EXTEST does the core board-interconnect test (drive outputs, capture inputs → opens/shorts, 10.1); SAMPLE/PRELOAD provides the non-intrusive snapshot (SAMPLE, observe) and the critical setup step (PRELOAD); and BYPASS lets you skip chips to manage the board chain efficiently. The single most important operational rule is the one the story teaches: EXTEST drives whatever the boundary cells hold, so you must PRELOAD known values before EXTEST — which is precisely why SAMPLE/PRELOAD is mandatory, and why skipping it produces undefined drive, contention, and garbage that masquerades as bad boards. The optional instructions extend the reach: IDCODE verifies the right device, INTEST (now largely superseded by scan/ATPG) tests internals, and — most consequentially — user/private instructions are the standard doorway to on-chip features, making JTAG the universal in-system access: start BIST and read the LBIST/MBIST signature (the direct 9.5 bridge — this is how the in-field self-test of Chapters 8–9 is commanded and read), program flash (ISP), and debug. For the DFT engineer, the mandatory set + BSDL is a compliance deliverable, and user instructions are how the SoC's BIST/debug features become accessible; for the board-test engineer, the PRELOAD → EXTEST → compare (with BYPASS for non-targets) is the interconnect-test recipe; and for the system engineer, the user instructions are the access they build on. These instructions are the verbs the board/in-system operations (10.5) and the worked path (10.6) use to actually test and access the mini-SoC.

13. Engineering Checklist

  • Implemented the mandatory instructions (BYPASS, SAMPLE/PRELOAD, EXTEST) for 1149.1 compliance.
  • PRELOAD before EXTEST (known/safe drive values) in every interconnect test.
  • BYPASS non-target chips; used IDCODE to verify devices.
  • Exposed on-chip BIST/ISP/debug via user instructions (in-system access, 9.5).
  • Documented the full instruction set in BSDL for board-test tools.

14. Try Yourself

  1. For each instruction (BYPASS/SAMPLE/PRELOAD/EXTEST/IDCODE/user), state which register it selects and its operation.
  2. Write the interconnect-test sequence: PRELOAD known values → BYPASS non-targets → EXTEST → shift/compare.
  3. Show what happens with EXTEST without PRELOAD (undefined drive → contention/garbage).
  4. Contrast EXTEST (between chips) with INTEST (internal) and why INTEST is rare (scan/ATPG).
  5. Describe a user instruction that starts BIST and reads the signature (the 9.5 bridge).

The instructions are IEEE 1149.1; sequences are tool-neutral. No paid tool required to reason about them.

15. Interview Perspective

  • Weak: "JTAG has BYPASS, SAMPLE, and EXTEST instructions."
  • Good: "Each instruction selects a register and an operation — EXTEST drives/observes pins for interconnect test, BYPASS skips the chip, SAMPLE/PRELOAD snapshots and sets up."
  • Senior: "A JTAG instruction (in the IR) selects a data register and defines the boundary-cell operation. Mandatory: BYPASS (1-bit register → skip the chip, shorten the chain); SAMPLE/PRELOAD (BSR → SAMPLE snapshots the pins non-intrusively to observe, PRELOAD loads known drive values to set up); EXTEST (BSR → drive output pins + capture input pins → board interconnect test). Common: IDCODE (read device ID). INTEST exists but is rare (scan/ATPG do internals). And user instructions access on-chip BIST/ISP/debug — the in-system access (9.5). The key rule: PRELOAD before EXTEST — EXTEST drives whatever the cells hold, so without PRELOAD the outputs drive undefined values → contention/garbage. That's exactly why SAMPLE/PRELOAD is mandatory."

16. Interview / Review Questions

17. Key Takeaways

  • Every JTAG instruction (in the IR) does two things: selects which data register sits between TDI/TDO and defines the boundary-cell operation.
  • Mandatory instructions: BYPASS (1-bit register → skip the chip, shorten the chain); SAMPLE/PRELOAD (BSR → SAMPLE snapshots the pins non-intrusively to observe, PRELOAD loads known drive values to set up); EXTEST (BSR → drive output pins + capture input pins → board interconnect test).
  • You must PRELOAD known values before EXTEST (that's why SAMPLE/PRELOAD is mandatory) — else the output cells drive undefined values → contention/garbage (the classic EXTEST bug).
  • Common optional: IDCODE (read device ID; auto-selected at reset); INTEST (internal test — rare, superseded by scan/ATPG).
  • User/private instructions are the 9.5 bridge — they access on-chip features: run BIST and read the LBIST/MBIST signature, program flash (ISP), and debug — making JTAG the universal in-system access. Next: 10.5 — JTAG in board & in-system test.

18. Quick Revision

JTAG instructions. Each instruction (in the IR) selects a data register + defines the boundary-cell operation. Mandatory: BYPASS (1-bit register → SKIP the chip, shorten the chain); SAMPLE/PRELOAD (BSR → SAMPLE = snapshot pins non-intrusively/observe; PRELOAD = load KNOWN drive values, set up); EXTEST (BSR → DRIVE output pins + CAPTURE input pins → board INTERCONNECT test). Common: IDCODE (read device ID, auto-selected at reset). INTEST = internal test (RARE — scan/ATPG do internals). USER/private = access on-chip BIST (start + read signature, 9.5) / ISP / debug. RULE: PRELOAD before EXTEST (EXTEST drives whatever the cells hold → without PRELOAD = undefined drive → contention/garbage). Next: 10.5 — JTAG in board & in-system test.