DFT · Chapter 10 · Boundary Scan & JTAG — chapter closer
Working Example: A JTAG Boundary-Scan Path
This capstone traces a concrete JTAG boundary-scan operation end to end on the project's mini-SoC placed on a board, tying together the TAP, the boundary cells, the instructions, and the board chain. The setup is simple: one chip's output pin connects by a board net to another chip's input pin, and you test that interconnect for an open or short without any physical probe. Reset the TAP by holding mode select high for five clocks, load SAMPLE and preload a known drive value, then load EXTEST so one chip drives the net and the other captures it, with any other chip in bypass. Shifting out the captured value and comparing reveals a good net, an open, or a short. Finally a user instruction starts the chip's built-in self-test and reads its signature over the same four-wire port.
Intermediate14 min readDFTJTAGEXTESTBoundary ScanBIST Access
Chapter 10 · Section 10.6 · Boundary Scan & JTAG — chapter capstone
Project thread — the mini-SoC on a board: JTAG tests its interconnect (EXTEST) and starts/reads its BIST (9.5) over one 4-wire port, closing the access story.
1. Why Should I Learn This?
This is Chapter 10 (and 9.5) working together — a concrete JTAG path that tests the board and accesses the chip's BIST over one port.
- Reset the TAP → PRELOAD a known drive value → EXTEST (A drives, B captures) → compare (open/short).
- No physical probe — the board interconnect tested electronically (10.1).
- USER instruction → start BIST + read the signature (the 9.5 in-system access bridge).
- One 4-wire port does board test and self-test access — the whole access story.
2. Real Silicon Story — one port, two jobs
The mini-SoC went onto a dense board, and the team needed two things they couldn't get any other way: test the interconnect to the neighboring chip (a BGA net they couldn't probe), and trigger the mini-SoC's in-field self-test at the board/system level (the LBIST/MBIST of Chapters 8–9).
JTAG delivered both over the same 4-wire port. For the interconnect: reset → PRELOAD a known 1 on the driving chip's output cell → EXTEST (the driver drives the net, the receiver captures it) → shift out and compare — net OK or open/short, no probe. For the self-test: a USER instruction selected the register wired to the mini-SoC's BIST controller — write 'start,' poll 'done,' read the signature on TDO.
One serial port tested the board and ran the chip's self-test. Lesson: a JTAG boundary-scan path both tests the board interconnect electronically (EXTEST, no probe) and accesses on-chip BIST (USER instruction) — the complete test-and-access capability, on one chain, which is exactly how the in-field self-test of Chapters 8–9 is operated in-system.
3. Factory Perspective — the JTAG path through each lens
- What the board-test engineer sees: the reset → PRELOAD → EXTEST → compare sequence — interconnect test without a probe — plus USER → BIST to run/read the chip's self-test.
- What the yield engineer sees: interconnect defects (opens/shorts) now caught on hidden-pin boards, and on-chip defects caught by the JTAG-triggered BIST.
- What the RTL/DV / DFT engineer sees: their chip's 1149.1 compliance + BSDL + user instruction made this possible — the integration that pays off here.
- What the system engineer sees: the in-system access — JTAG starts/reads the mini-SoC's BIST (9.5), programs it (ISP), and debugs it — the operational doorway.
4. Concept — the end-to-end boundary-scan path
Setup:
- Chip A output pin PA — net X — Chip B input pin PB (mini-SoC is one of them); other chips BYPASSed (10.5).
The interconnect-test path (no probe):
- Reset (10.2): TMS=1 for 5 TCK → Test-Logic-Reset (known state); TMS=0 → Run-Test/Idle.
- Load SAMPLE/PRELOAD (Shift-IR) and PRELOAD (Shift-DR): set chip A's output boundary cell for PA to drive 1 — a known value before EXTEST (mandatory, 10.4).
- Load EXTEST (Shift-IR) into A and B (BYPASS others): entering EXTEST, A drives net X = 1 (its update flop), B captures net X at PB's input cell.
- Shift out B's captured value (Shift-DR → TDO) and compare:
- A drove 1, B captured 1 → net OK.
- B captured 0 → OPEN (or short to ground).
- Two nets both capture a wrong/shared value → SHORT between them.
The BIST-access path (the 9.5 bridge):
- Load a USER instruction (Shift-IR) → selects a user data register wired to the chip's BIST controller.
- Write 'start LBIST/MBIST', poll 'done', read the signature / go-nogo (Shift-DR → TDO) → in-system self-test access.
- Other in-system uses over the same port: ISP (program flash), debug.
The result:
- One 4-wire JTAG port tested the board interconnect (electronically, no probe) and accessed the on-chip BIST — the complete test-and-access story (10.1/10.5), and how the in-field BIST of Chapters 8–9 is operated.
5. Mental Model — a control-room test of a sealed pipe, then a self-check
The whole path is like a control-room operator testing a sealed pipe between two buildings, then asking a building to run its own diagnostics — all from one console.
- Reset: the operator puts the console in a known mode (Test-Logic-Reset) so commands mean what they should.
- PRELOAD: they set the valve at building A's outlet to 'send water' (drive 1) — staged, but not yet live.
- EXTEST: they go live — building A sends water down the sealed pipe (net X), and building B's sensor reads what arrives. Water arrives → pipe OK; nothing arrives → a blockage (open); water shows in the wrong pipe → a cross-connection (short) — all without opening a wall (no probe).
- USER → BIST: then, over the same console, they tell building B to run its internal self-check and report the result — the in-system self-test access.
- One console (the 4-wire TAP) both tests the hidden pipe and runs the building's diagnostics — the complete job.
Set a known mode, stage the drive, go live, read the far sensor — then ask for a self-check — all from one console: that's a JTAG boundary-scan path.
6. Working Example — the full sequence
The interconnect test and BIST access, end to end:
# JTAG boundary-scan interconnect test - REPRESENTATIVE, SIMPLIFIED, tool-neutral (Chip A PA -- net X -- Chip B PB):
1) RESET: TMS=1 x5 (TCK) -> Test-Logic-Reset ; TMS=0 -> Run-Test/Idle (10.2 -- known state first)
2) SAMPLE/PRELOAD: Shift-IR: load SAMPLE/PRELOAD ; Shift-DR: PRELOAD A's PA output cell = drive 1 (10.4)
3) EXTEST: Shift-IR: load EXTEST into A + B (BYPASS others, 10.5)
-> A DRIVES net X = 1 ; B CAPTURES net X at PB
4) READ + COMPARE: Shift-DR: shift B's boundary register out on TDO
B captured 1 -> NET X OK
B captured 0 -> OPEN (or short to gnd) -> DEFECT (no physical probe!)
two nets share a wrong value -> SHORT between them
# Board INTERCONNECT tested electronically. Chip INTERNALS were tested by scan/ATPG + BIST (Ch3-9).# BIST access via a USER instruction - the 9.5 bridge (close the loop) - REPRESENTATIVE:
5) USER (BIST): Shift-IR: load a USER instruction -> selects the register wired to the on-chip BIST controller
Shift-DR: write 'start LBIST/MBIST' ; poll 'done' ; read SIGNATURE / go-nogo on TDO
-> in-system self-test: this is HOW the in-field BIST of Ch8/9 is TRIGGERED + READ over JTAG
RESULT: ONE 4-wire TAP tested the board interconnect AND accessed the on-chip BIST -> the whole access story.The waveform shows the serial shifting and the net drive/capture:
JTAG path: reset (TMS) → Shift-IR (load) → Shift-DR (EXTEST net drive/capture) → TDO compare → USER/BIST
10 cycles7. Industry Flow — the path closes the test-access arc
This path unites board interconnect test and in-system BIST access, the end of the DFT access story:
8. Debugging Session — interconnect test fails on a good board
A JTAG interconnect test reports a fail on a known-good board, and the team suspects a solder defect; either the boundary cells were not PRELOADed before EXTEST (so the driver drove an undefined value) or the TAP was not reset to a known state first, so the operation was invalid -- the fix is to apply the disciplines in order: reset the TAP, PRELOAD known drive values, then EXTEST, after which a true fail is a real open/short
RESET FIRST, PRELOAD BEFORE EXTEST — OR A GOOD BOARD 'FAILS' THE INTERCONNECT TESTA JTAG interconnect test reports a FAIL on a known-good board (verified good otherwise). The team suspects a solder defect and is about to rework the board.
The interconnect test was invalid because of a sequencing error — either the boundary cells were not PRELOADed before EXTEST (so the driver drove an undefined value onto the net) or the TAP was never reset to a known state — so the 'fail' reflects the broken procedure, not a board defect. Two disciplines from earlier lessons are preconditions for a valid boundary-scan interconnect test, and skipping either produces a false fail on a good board: (1) PRELOAD before EXTEST (10.4) — EXTEST drives whatever the boundary cells hold, so without a prior PRELOAD of the driver's output cell to a known value (here, 1), chip A drives an undefined value onto net X; the receiver B then captures an arbitrary value that won't match the expected pattern → a compare fail that has nothing to do with the net's integrity. (2) Reset the TAP first (10.2) — the TAP is a stateful FSM, so if the session didn't begin with the 5-TMS-high reset to Test-Logic-Reset, the navigation to Shift-IR/Shift-DR may have started from the wrong state, so the instructions/data landed in the wrong states and the whole operation is meaningless. In both cases the board is fine; the procedure was wrong — and 'reworking' a good board would waste effort and not fix the (non-existent) defect.
Apply the disciplines in order — reset the TAP, PRELOAD known drive values, then EXTEST — and re-run; a fail after that is a real open/short. Begin with the guaranteed reset (TMS=1 for 5 TCK → Test-Logic-Reset, 10.2) so navigation starts from a known state. Load SAMPLE/PRELOAD and PRELOAD the driver's output boundary cell to the known drive value (1 on PA), and BYPASS non-target chips (10.5). Then load EXTEST so chip A drives net X = 1 and chip B captures it, shift out B's value, and compare. With the sequence correct, the result is trustworthy: captured 1 → net OK; captured 0 → a real OPEN (or short to gnd); two nets sharing a wrong value → a real SHORT — now worth investigating as a solder defect. The principle to lock in: a JTAG boundary-scan interconnect test drives one chip's output pin and captures the connected chip's input pin under EXTEST to detect opens and shorts without a physical probe, but it is only valid if the TAP is first reset to a known state and the boundary cells are PRELOADed to known drive values before EXTEST; a fail on a known-good board is almost always a procedure error (no reset, or EXTEST without PRELOAD) making the driver drive an undefined value, so apply reset then PRELOAD then EXTEST, after which a genuine mismatch is a real interconnect defect — and the same TAP, via a user instruction, starts and reads the on-chip BIST, so one 4-wire port both tests the board and accesses the chip's self-test. (Reset/navigation is 10.2; PRELOAD/EXTEST is 10.4; chain composition/BYPASS is 10.5; BIST access ties to 9.5.)
9. Common Mistakes
- EXTEST without PRELOAD. The driver drives an undefined value → false fail — PRELOAD known values first (10.4).
- Not resetting the TAP first. Navigation from an unknown state is meaningless — 5 TMS-high clocks → Test-Logic-Reset (10.2).
- Reworking a good board on a false fail. Verify the sequence (reset/PRELOAD/EXTEST) before suspecting solder.
- Forgetting to BYPASS non-targets. Wrong chain composition → operations mis-address (10.5).
- Missing the BIST-access bonus. A USER instruction starts/reads BIST over the same port (9.5) — use it.
10. Industry Best Practices
- Sequence: reset → PRELOAD → EXTEST → compare — every interconnect test.
- BYPASS non-target chips; compose the chain correctly (10.5); verify with IDCODE.
- Use a USER instruction for in-system BIST (start + read signature, 9.5) over the same port.
- Trust a fail only after the sequence is correct — don't rework a good board on a false fail.
- Rely on accurate BSDL (10.3) for cells, pin mapping, and IR lengths.
11. Senior Engineer Thinking
- Beginner: "The interconnect test failed — rework the solder joint."
- Senior: "Did we reset the TAP and PRELOAD before EXTEST? Without PRELOAD, the driver drives an undefined value → the receiver captures garbage → false fail on a good board. I run reset → PRELOAD → EXTEST → compare; then a mismatch is a real open/short. And I use the same port with a USER instruction to start/read the chip's BIST (9.5). One port, two jobs — done right."
The senior verifies the sequence (reset/PRELOAD/EXTEST) before trusting a fail, and uses one port for test + BIST access.
12. Silicon Impact
This capstone makes the whole JTAG story concrete and closes the DFT test-access arc: over one 4-wire port, boundary scan tests the board interconnect (drive one chip's pin, capture the connected chip's pin under EXTEST → opens/shorts, no physical probe — the killer app of 10.1) and accesses the on-chip BIST (a USER instruction starts LBIST/MBIST and reads the signature — the direct 9.5 bridge). It demonstrates that JTAG is how the in-field self-test of Chapters 8–9 is operated in-system, and that one interface serves both board test and chip self-test — a striking economy of access. The operational disciplines the debugging session drives home are the ones that separate a valid result from a false one: reset the TAP to a known state first (10.2 — the FSM is stateful) and PRELOAD known drive values before EXTEST (10.4 — EXTEST drives whatever the cells hold), because skipping either produces a false fail on a good board, and 'reworking' that board wastes effort on a non-existent defect. Get the sequence right — reset → PRELOAD → EXTEST → compare (with BYPASS for non-targets, 10.5) — and a mismatch is a real interconnect defect worth investigating. This path is the payoff of the chapter's integration: the chip's 1149.1 compliance, boundary cells, BSDL, and user instructions (10.2–10.5) come together so a board tester (or the system itself) can test the interconnect and run/read the self-test from four wires. It completes the DFT big picture — inside the chip (scan/ATPG/BIST, Chapters 3–9), between the chips (interconnect), and in-system access (JTAG) — and hands off to Chapter 11 (Test Modes & DFT Signals), which organizes the test-mode / scan-enable / BIST-enable controls that all of these mechanisms depend on. For the RTL/DV / DFT engineer, the lasting lesson is that boundary scan + JTAG turn a hidden-pin, self-testing SoC into one that is fully testable, accessible, and debuggable on a real board — the operational endpoint of everything DFT builds.
13. Engineering Checklist
- Reset the TAP (5 TMS-high clocks → Test-Logic-Reset) before the sequence.
- PRELOAD the driver's output cell to a known value before EXTEST; BYPASS non-targets.
- Ran EXTEST (drive/capture the net), shifted out, and compared (OK/open/short).
- Used a USER instruction to start/read the on-chip BIST (9.5) over the same port.
- Trusted a fail only after the sequence was correct — didn't rework a good board on a false fail.
14. Try Yourself
- Set up Chip A PA — net X — Chip B PB; add boundary cells and the 4-wire TAP.
- Write the sequence: reset → PRELOAD (drive 1) → EXTEST → shift out → compare (OK/open/short).
- Show a false fail from EXTEST without PRELOAD (undefined drive) — and fix it.
- Use a USER instruction to start BIST and read the signature (the 9.5 bridge).
- Explain how one 4-wire port does both board interconnect test and on-chip BIST access.
The path is IEEE 1149.1; sequences are tool-neutral. A JTAG controller drives it in practice. No paid tool required to trace it.
15. Interview Perspective
- Weak: "You use JTAG to test the board connections."
- Good: "Drive a pin on one chip and capture it on another with EXTEST to test the net, after resetting and preloading."
- Senior: "The full path: reset the TAP (5 TMS-high → Test-Logic-Reset), load SAMPLE/PRELOAD and PRELOAD the driver's output cell to a known 1 (before EXTEST), BYPASS non-targets, then load EXTEST so chip A drives net X and chip B captures it; shift out and compare — 1 → OK, 0 → open (or short to gnd), two nets sharing a wrong value → short — all with no physical probe. The disciplines: reset first and PRELOAD before EXTEST, or a good board false-fails. Then the 9.5 bridge: a USER instruction on the same port starts the chip's LBIST/MBIST and reads the signature — in-system self-test access. So one 4-wire JTAG port both tests the board interconnect and accesses the on-chip BIST — the complete test-and-access story."
16. Interview / Review Questions
17. Key Takeaways
- A JTAG boundary-scan path tests a board net between two chips: reset the TAP → PRELOAD the driver's output cell to a known value → EXTEST (driver drives the net, receiver captures it) → shift out and compare → OK / open / short — without any physical probe (10.1).
- The disciplines are mandatory: reset the TAP first (10.2 — stateful FSM) and PRELOAD before EXTEST (10.4 — EXTEST drives whatever the cells hold); skipping either false-fails a good board.
- The same 4-wire TAP provides in-system BIST access — a USER instruction starts LBIST/MBIST and reads the signature (the 9.5 bridge) — so one port does board interconnect test and chip self-test access.
- This closes the DFT test-access arc: inside the chip (scan/ATPG/BIST, Ch3–9), between the chips (interconnect), and in-system access (JTAG) — the complete test-and-access picture.
- It's the payoff of 1149.1 integration (TAP + cells + BSDL + user instructions, 10.2–10.5), and it sets up Chapter 11 (Test Modes & DFT Signals) — organizing the test-mode/scan-enable/BIST-enable controls all these mechanisms rely on. Next: Chapter 11 — Test Modes & DFT Signals.
18. Quick Revision
A JTAG boundary-scan path (Ch10 capstone). Test a board net between two chips WITHOUT a probe: RESET (5 TMS=1 → Test-Logic-Reset, 10.2) → SAMPLE/PRELOAD + PRELOAD the driver's output cell = drive 1 (known value BEFORE EXTEST, 10.4) → BYPASS non-targets (10.5) → EXTEST (A DRIVES net X, B CAPTURES it) → shift out on TDO + COMPARE: 1=OK, 0=OPEN (or short-to-gnd), two nets sharing a wrong value=SHORT. Disciplines: reset first + PRELOAD before EXTEST, or a GOOD board FALSE-FAILS. 9.5 bridge: a USER instruction on the same port starts LBIST/MBIST + reads the signature → in-system self-test access. ONE 4-wire TAP = board interconnect test AND on-chip BIST access. Closes the DFT access arc (inside chip + between chips + in-system). Next: Chapter 11 — Test Modes & DFT Signals.