Shift & Capture Timing

Chapter 12 · Section 12.2 · DFT Constraints & Timing

Project thread — the mini-SoC's scan test needs both shift-path hold and capture-path setup closed; 12.3 adds scan-enable timing, 12.4 the at-speed capture.

1. Why Should I Learn This?

Scan test has two operations with opposite timing concerns — knowing which is which is the fastest path to fixing a scan-timing bug.

• Shift = a HOLD problem: adjacent scan cells clocked together on a slow clock → setup easy, hold hard (skew → lock-up latches, 4.2).
• Capture = a SETUP problem: the combinational logic between flops must meet setup at the functional/at-speed clock.
• Different paths: shift path (Q→SI) in shift mode; capture path (flop→logic→flop) in capture mode.
• Don't confuse them: a shift-hold race isn't fixed by a setup change (shift is slow).

2. Real Silicon Story — a shift-hold race fixed with a setup change (that didn't work)

A chip had intermittent chain-integrity fails (3.3) — some dies couldn't reliably shift a known pattern. The team, seeing a shift problem, tried to slow the shift clock further and relax setup, assuming a setup issue. It didn't help.

The bug was a hold race on the shift path. Adjacent scan cells were clocked with enough skew that the launching cell's shifted value raced into the receiving cell too fast — a hold violation — so the receiving cell captured the new value instead of holding the old, corrupting the shift. Since shift already ran on a slow clock, setup was never the problem — slowing the clock more did nothing, because hold violations don't care about clock period (they're about the race between adjacent cells, not the cycle time).

The fix was a lock-up latch (4.2) at the skew boundary (and better shift-clock skew balancing) to retime the shift data so the receiving cell samples a stable value. Lesson: shift is a hold problem, not a setup one — slowing the clock (a setup fix) won't fix a shift-hold race; you need a hold fix (lock-up latch / skew balancing). Diagnosing shift = hold vs capture = setup is what points you at the right fix.

3. Factory Perspective — shift/capture timing through each lens

• What the STA/timing engineer sees: two analyses — the shift-path hold (slow clock, adjacent cells) and the capture-path setup (functional/at-speed clock) — on different paths in different modes.
• What the CTS/physical engineer sees: the shift-clock skew and lock-up latches (hold), and the capture-clock timing on the functional paths (setup).
• What the RTL/DV engineer sees: that the capture path is their functional path (setup), while the shift path is a DFT structure (hold) they don't design but must be closed.
• What management cares about: that both must close — shift-hold (or chains fail integrity) and capture-setup (or responses are wrong) — a schedule risk if one is missed.

4. Concept — shift (hold) vs capture (setup)

Shift timing — a HOLD problem:

• In shift mode, the chain is a shift register: cell.Q → next cell.SI (3.3), all clocked on the same (shift) clock edge.
• Adjacent cells clocked ~together → the shifted value must not reach the next cell too fast → a hold requirement between adjacent cells.
• Slow shift clock → setup is easy (lots of time); hold is the concern, and clock skew between adjacent cells makes it worse (the launching value races into the receiving cell) → lock-up latches (4.2) retime the shift data at skew/domain boundaries.
• Hold doesn't depend on clock period — slowing the clock doesn't fix a hold race (the story).

Capture timing — a SETUP problem:

• In capture mode, one functional clock fires; the combinational logic between scan flops must settle and meet setup at the capture clock — exactly like functional timing.
• Stuck-at: slow capture → setup easy. At-speed (transition): rated-clock capture → setup is the real functional critical-path timing (12.4).

Different paths, different modes:

• Shift path (Q→SI): analyzed only in shift mode (hold, slow clock).
• Capture path (flop → logic → flop): the functional path, analyzed in capture mode (setup, functional/at-speed clock).

The clean contrast:

• Shift = hold (adjacent cells, slow clock, lock-up latches).
• Capture = setup (combinational logic, functional/at-speed clock).

5. Mental Model — a bucket brigade vs a single relay throw

Shift and capture are like two different timing games in the same crew.

• Shift is a bucket brigade passing buckets hand to hand down a line, all on the same beat (the slow shift clock). The danger is not that a bucket arrives too late (there's plenty of time — setup is easy) — it's that a fast passer shoves the bucket into the next person before they've secured theirs (a hold race), especially if some people are slightly off-beat (clock skew). You fix it by adding a brief pause between two people (a lock-up latch), not by slowing the whole line down (which doesn't fix the shove).
• Capture is a single, precise relay throw through an obstacle course (the combinational logic) that must reach the target before the whistle (the capture edge). Here the danger is arriving too late (setup) — the throw must clear the course in time. At a slow whistle (stuck-at) it's easy; at a fast whistle (at-speed) it's the real challenge (the functional critical path).
• The lesson: a shove in the brigade (shift-hold) and a late throw (capture-setup) are different failures needing different fixes — a pause vs a faster/shorter course.

Brigade shoves are hold races (add a pause); the relay throw is a setup deadline (clear the course in time) — different games, different fixes.

6. Working Example — the two analyses

Contrast the shift and capture timing analyses:

# Shift vs capture timing - REPRESENTATIVE, SIMPLIFIED, tool-neutral:
  SHIFT mode:
    path: cell[k].Q -> cell[k+1].SI   (adjacent scan cells, SAME shift clock edge)
    clock: SHIFT clock (SLOW)          -> SETUP margin is LARGE (easy)
    concern: HOLD -- cell[k]'s new Q must NOT reach cell[k+1] before it safely holds (a race)
    skew makes it worse -> FIX: LOCK-UP LATCH (4.2) at skew/domain boundaries ; balance shift-clock skew
    NOTE: hold does NOT depend on clock period -> slowing the shift clock does NOT fix a shift-hold race
  CAPTURE mode:
    path: flop -> combinational logic -> flop   (the FUNCTIONAL path)
    clock: functional / AT-SPEED capture clock
    concern: SETUP -- the logic must settle before the capture edge
    stuck-at: SLOW capture -> setup easy ; at-speed: RATED clock -> setup IS the functional critical path (12.4)
# SHIFT = HOLD (adjacent cells, slow clock, lock-up latch) ; CAPTURE = SETUP (logic, functional/at-speed clock).

The waveform shows the two clocking regimes:

7. Industry Flow — close shift hold and capture setup

Scan timing closes two distinct analyses in two modes:

8. Debugging Session — chain shifts wrong data, blamed on setup

9. Common Mistakes

• Treating a shift-hold race as a setup issue. Slowing the clock won't fix hold (period-independent) — use a lock-up latch (4.2).
• Ignoring shift-clock skew. Adjacent-cell skew drives shift-path hold races — balance it / add lock-up latches.
• Assuming capture is easy because shift is slow. Capture is a setup problem at the functional/at-speed clock (12.4).
• Analyzing one path in both modes. Shift path (Q→SI) and capture path (flop→logic→flop) are different analyses.
• Closing only capture. Both must close — shift-hold (chain integrity) and capture-setup (valid response).

10. Industry Best Practices

• Close shift-path hold — balance shift-clock skew; lock-up latches at skew/domain boundaries (4.2).
• Close capture-path setup — the functional/at-speed critical path (12.4).
• Analyze each in its own mode — shift path (shift mode), capture path (capture mode).
• Diagnose shift-hold vs capture-setup before fixing — they need different fixes.
• Keep the shift clock fast — fix hold with lock-up latches, not a slower clock (test time, 1.4).

11. Senior Engineer Thinking

• Beginner: "The chain shifts wrong data — slow the shift clock to fix the timing."
• Senior: "Shift is a hold problem, not setup — slowing the clock does nothing (hold is period-independent). Adjacent cells with skew let the value race into the next cell. I add a lock-up latch (4.2) / balance the skew. And I keep that separate from capture, which is a setup problem on the logic at the functional/at-speed clock. Shift = hold; capture = setup."

The senior diagnoses shift = hold vs capture = setup and applies the right fix (lock-up latch vs faster path).

12. Silicon Impact

Shift and capture timing is a small idea with big practical payoff: the two operations of a scan test have opposite timing concerns, and knowing which is which points you straight at the right fix. Shift is a hold problem — the chain is a shift register with adjacent cells clocked together on a slow clock, so setup is easy but the shifted value can race into the next cell (a hold violation, worsened by clock skew), and — the crucial, counterintuitive part — hold is independent of the clock period, so slowing the shift clock does nothing (the story); the correct fix is a lock-up latch (4.2) or skew balancing. Capture is a setup problem — the combinational logic between flops must settle and meet setup at the functional/at-speed clock, which for at-speed test is the real functional critical path (12.4). They also analyze different paths in different modes — the shift path (Q→SI) only in shift mode, the capture path (flop→logic→flop) in capture mode — two separate analyses, both of which must close (or the chains fail integrity / the captured response is wrong). The most common, most wasteful mistake is conflating them — trying to fix a shift-hold race with a setup/clock-period change (useless) or chasing a capture-setup miss as if it were a shift problem — so the diagnostic discipline (shift = hold, capture = setup) is what turns a mysterious 'scan timing bug' into a targeted fix. For the STA/CTS engineer, this means two distinct closures — shift-clock skew + lock-up latches for hold, and the functional/at-speed capture path for setup; for the RTL/DV engineer, the capture path is their functional path (setup), which their optimizations help. This distinction underpins scan-enable timing (12.3) and at-speed capture (12.4), and it's a core piece of the per-mode STA constraints (12.5) that make the Chapter 11 modes timing-close in silicon.

13. Engineering Checklist

• Closed shift-path hold — balanced shift-clock skew; lock-up latches at skew/domain boundaries (4.2).
• Closed capture-path setup — the functional/at-speed critical path (12.4).
• Analyzed shift path (shift mode) and capture path (capture mode) as separate analyses.
• Diagnosed shift-hold vs capture-setup before fixing (right fix per failure).
• Kept the shift clock fast (hold fixed with lock-up latches, not a slower clock — test time, 1.4).

14. Try Yourself

1. Draw the shift path (cell.Q → next cell.SI) and explain why it's a hold problem on a slow clock.
2. Show a hold race from clock skew between adjacent cells → fix with a lock-up latch (4.2).
3. Explain why slowing the shift clock does not fix a shift-hold race (hold is period-independent).
4. Draw the capture path (flop → logic → flop) and explain why it's a setup problem at the functional/at-speed clock.
5. Diagnose a scan-timing failure as shift-hold vs capture-setup and give the matching fix.

The analyses are tool-neutral; lock-up latches are standard. No paid tool required to reason about shift/capture timing.

15. Interview Perspective

• Weak: "Scan has shift and capture; both need timing closure."
• Good: "Shift is a hold problem between adjacent cells; capture is a setup problem on the logic."
• Senior: "The two scan operations have opposite timing concerns. Shift is a hold problem: the chain is a shift register with adjacent cells clocked together on a slow clock, so setup is easy but the shifted value can race into the next cell — a hold violation, worse with clock skew — fixed by a lock-up latch (4.2) or skew balancing. And hold is independent of the clock period, so slowing the shift clock doesn't fix it. Capture is a setup problem: the combinational logic between flops must settle and meet setup at the functional/at-speed clock — at-speed, that is the functional critical path. They're different paths in different modes — shift path (Q→SI) vs capture path (flop→logic→flop). So I diagnose shift-hold vs capture-setup first, because they need different fixes — a lock-up latch vs a faster path."

16. Interview / Review Questions

17. Key Takeaways

• The two operations of a scan test have opposite timing concerns: shift is a hold problem and capture is a setup problem.
• Shift = hold: the chain is a shift register with adjacent cells clocked together on a slow clock — so setup is easy but the shifted value can race into the next cell (a hold violation, worsened by clock skew), fixed by lock-up latches (4.2) or skew balancing — not by slowing the clock (hold is period-independent).
• Capture = setup: the combinational logic between scan flops must settle and meet setup at the functional/at-speed clock — easy for stuck-at (slow capture), hardest at at-speed (the real functional critical path, 12.4).
• They analyze different paths in different modes — the shift path (Q→SI) in shift mode, the capture path (flop→logic→flop) in capture mode — two separate analyses, both of which must close.
• Diagnose shift-hold vs capture-setup before fixing — they need different fixes (a lock-up latch vs a faster/shorter path); conflating them is the classic scan-timing mistake. Next: 12.3 — scan-enable timing & setup/hold.

18. Quick Revision

Shift & capture timing. Two scan operations, OPPOSITE concerns. SHIFT = a HOLD problem: chain = shift register (cell.Q → next cell.SI), adjacent cells clocked TOGETHER on a SLOW clock → setup EASY, but the shifted value can RACE into the next cell (HOLD violation, worse with clock SKEW) → fix with LOCK-UP LATCHES (4.2) / skew balancing, NOT by slowing the clock (hold is period-INDEPENDENT). CAPTURE = a SETUP problem: combinational logic BETWEEN flops must settle + meet SETUP at the functional/at-speed clock (easy for stuck-at slow capture; hardest at at-speed = the functional critical path, 12.4). Different PATHS in different MODES (shift path vs capture path); both must close. Diagnose shift-hold vs capture-setup first → different fixes (lock-up latch vs faster path). Next: 12.3 — scan-enable timing & setup/hold.