DFT Constraints for STA

Chapter 12 · Section 12.5 · DFT Constraints & Timing — chapter closer

Project thread — the mini-SoC's multi-mode timing signoff: functional, shift, and capture-at-speed each constrained and closed. This closes Chapter 12 and sets up Chapter 13 (DFT debug).

1. Why Should I Learn This?

DFT constraints for STA are how the whole chapter's timing becomes real: you tell STA about each test mode so it can verify the design is test-clean, not just functional-clean.

• Multi-mode STA: functional / shift / capture-at-speed are different timing problems → analyze each separately.
• set_case_analysis selects the mode topology (test_mode=1 scan on; scan_enable=1 shift vs =0 capture).
• Per-mode clocks (slow shift clock; fast functional/at-speed + OCC pulses) and exceptions (false/multicycle honored at-speed; SE setup/hold; I/O for boundary scan).
• Signoff: all modes clean = test-clean — functional-clean alone is not enough (12.1). Bridge to Ch13 (debug).

2. Real Silicon Story — the mode nobody constrained

A chip was functional-clean and taped out — every functional path closed. In silicon, scan test failed: chain miscompares that looked random. The logic was fine; functional timing was fine.

The cause was a mode nobody constrained. The team had closed the functional mode in STA, but had never set up the shift mode — no slow shift clock, no scan_enable = 1 case analysis, no HOLD checks across adjacent scan cells (12.2). So the shift path's hold violations (adjacent cells clocked together, 12.2) were invisible to STA and shipped — surfacing as shift miscompares in silicon (that's why lock-up latches / clock skew balancing exist, 4.x). The fix was to add the missing modes' SDC: a shift run (slow clock, scan_enable=1, hold checks) and a capture-at-speed run (functional/at-speed clock, scan_enable=0, setup at the functional period, honoring false/multicycle) — then close all modes. Only then was the design test-clean. Lesson: functional-clean is not test-clean — each test mode (shift, capture, at-speed) is a separate STA problem with its own clocks, case analysis, and exceptions, and all of them must be constrained and closed or the untimed mode fails in silicon.

3. Factory Perspective — DFT constraints through each lens

• What the STA/timing engineer sees: multiple scenarios/runs (functional/shift/capture-at-speed), each with its own SDC (case analysis, clocks, exceptions) — the core deliverable.
• What the DFT engineer sees: that the modes they built (scan, OCC, SE, boundary scan) are only valid if constrained — DFT supplies the mode definitions STA uses.
• What the RTL/DV engineer sees: that false paths/multicycles they know functionally must be carried into the at-speed run, or they become false at-speed fails (12.4).
• What management cares about: that signoff means all modes clean (test-clean, not just functional-clean) — the difference between a working test program and silent test escapes/miscompares.

4. Concept — multi-mode STA via SDC

The principle — analyze each mode separately:

• Functional, shift, and capture-at-speed are different timing problems (different clocks, topology, and checks) — the reasoning behind that claim is why DFT affects timing.
• So each is analyzed in its own run/scenario with its own SDC. A design clean in one mode can violate in another (12.1).

Select the mode — set_case_analysis:

• Pin test_mode / scan_enable to a constant so STA sees the right topology:
  • test_mode = 1 → scan muxes / OCC test path are on (test configuration).
  • scan_enable = 1 → shift configuration (flop D = SI); scan_enable = 0 → capture configuration (flop D = functional).

Define per-mode clocks:

• Shift run: a slow shift clock (create_clock on the test clock).
• Capture run: the fast functional/at-speed clock(s) and the OCC-generated pulses (create_generated_clock on the OCC output) — the launch/capture pair (12.4).

Add exceptions:

• set_false_path / set_multicycle_path to honor functional false/multicycle paths in the capture-at-speed run (so they don't become false at-speed fails, 12.4).
• set_false_path between clocks that never interact in a given mode.
• Constrain SE (12.3): its setup/hold to the capture clock.
• set_input_delay / set_output_delay for boundary-scan I/O (10.x).

Close each mode — the right check:

• Shift run: slow clock, scan_enable=1 → check HOLD across adjacent scan cells (shift and capture timing). Hold does not improve with a slower clock, which is why this run cannot be skipped.
• Capture run: functional/at-speed clock, scan_enable=0 → check SETUP launch→capture at the functional period (at-speed test timing), honoring false/multicycle. scan_enable is a timed net here, not a constant — see scan-enable timing.

Signoff — the chapter's closing rule:

• ALL modes must be timing-clean — functional AND shift AND capture-at-speed. Only then is the design test-clean (not just functional-clean, 12.1). When a mode is not clean → DFT debug, Ch13.

5. Mental Model — one building, three fire-drills

The DFT SDC is like running three different fire-drills on one building, each with its own rules, before you certify it safe.

• The building is the one netlist. But you certify it for three scenarios: normal occupancy (functional), a slow evacuation (shift), and a fast, full-alarm evacuation (capture-at-speed). Each has different exits open (case analysis selects the topology), a different clock/timing (slow vs fast alarms), and different rules (HOLD for the slow drill, SETUP for the fast one).
• You can't certify the building safe just because normal occupancy is fine (functional-clean). The slow evacuation might have a jammed door (a shift hold violation) that only shows in that drill.
• You also honor the real floor-plan: some corridors are deliberately not through-routes (false paths / multicycles) — if you forget that in the fast drill, you get a false alarm (a false at-speed fail, 12.4).
• Only when all three drills pass do you certify the building (test-clean signoff). If one drill fails, you send in the inspectors (DFT debug, Ch13).

One building, three fire-drills with different rules (case analysis, per-mode clocks, hold-vs-setup) — certify safe only when all pass; functional occupancy being fine is not certification.

6. Working Example — the per-mode SDC (representative)

Section 4 states the rule that governs this file: each mode is analysed in its own run with its own SDC. That is not a stylistic preference, and it is worth being concrete about why, because the tempting shortcut is to put all three modes in one script.

They cannot coexist in one file. Shift needs set_case_analysis 1 on scan_enable and capture needs 0. A single script containing both does not analyse two modes — it applies the last one and silently discards the first, because case analysis is a property of the run, not a section of the file. The same applies to the clocks: a slow shift clock and a fast OCC-gated capture clock defined on the same design describe two different timing problems, and STA has no notion of "these two are alternatives".

So the constraints below are three files, loaded by three separate runs.

# ============================================================================
#  RUN 1 of 3 — FUNCTIONAL (mission). Representative, tool-neutral.
# ============================================================================
 
# DFT is off. Case analysis prunes the test topology so STA sees the mission
# design: scan muxes select their functional input, the OCC is bypassed.
set_case_analysis 0 [get_ports test_mode]
set_case_analysis 0 [get_ports scan_enable]
 
create_clock -name clk_core -period 2.000 [get_ports CLK]      ;# 500 MHz mission
 
# The scan mux delay is NOT excluded here. It sits in the D path of every scan
# flop and is analysed as part of the functional path - that is the mission-mode
# cost of scan insertion, and it must be budgeted, not constrained away.
 
set_input_delay  -max 0.6 -clock clk_core [remove_from_collection \
                    [all_inputs] [get_ports CLK]]
set_output_delay -max 0.6 -clock clk_core [all_outputs]

# ============================================================================
#  RUN 2 of 3 — SCAN SHIFT. Slow clock; the analysis that matters is HOLD.
# ============================================================================
 
set_case_analysis 1 [get_ports test_mode]
set_case_analysis 1 [get_ports scan_enable]     ;# flop D = SI: the chain is live
 
# The tester's shift clock. Slow by design, to keep shift power manageable.
create_clock -name clk_shift -period 20.000 [get_ports test_clk]
 
# With scan_enable tied high the functional cone is inactive and the only live
# paths run cell -> cell along the stitched order. The 20 ns period makes SETUP
# on those paths trivial and does nothing whatsoever for HOLD, which is
# frequency-independent - so this run exists to close hold.
# See /dft/why-dft-affects-timing for why slowing the clock cannot fix hold.
 
# Lock-up latches inserted at chain clock-domain crossings appear as ordinary
# level-sensitive elements here; do not false-path them, they are the fix.
 
# The functional clock does not exist in this run, so no exception is needed to
# separate it from clk_shift. That is a benefit of per-mode files: mode-exclusive
# clocks cannot interact because only one of them is defined.

# ============================================================================
#  RUN 3 of 3 — CAPTURE AT-SPEED. Functional paths, rated clock, SE is timed.
# ============================================================================
 
set_case_analysis 1 [get_ports test_mode]
# scan_enable is deliberately NOT case-analysed here. It falls between the last
# shift pulse and the capture pulse, so it is a timed net in this run.
 
create_clock -name clk_ref -period 2.000 [get_ports pll_ref]
 
# The on-chip clock controller gates the fast clock into the launch/capture
# pulse pair. STA must see the pulses, not the free-running reference.
create_generated_clock -name occ_cap -source [get_ports pll_ref] -divide_by 1 \
    [get_pins occ/cap_clk_out]
 
# ---- Scan-enable timing (this is the constraint Section 4 calls for) -------
# SE must be settled before the capture edge. Constrain it as an input against
# the capture clock rather than leaving it unconstrained.
set_input_delay -max 0.4 -clock occ_cap [get_ports scan_enable]
 
# Broadside (launch-on-capture): launch and capture are a functional cycle
# apart, so SE has a full cycle to settle and the path is relaxed.
set_multicycle_path -setup 2 -from [get_ports scan_enable]
set_multicycle_path -hold  1 -from [get_ports scan_enable]
#
# Launch-off-shift would DELETE the two lines above: there SE must switch at the
# rated clock, which is what makes high-fanout SE distribution an at-speed
# problem. Copying these exceptions between projects without checking the
# pattern style hides a real at-speed failure.
 
# ---- Functional exceptions, honoured in the at-speed run -------------------
# A path that is genuinely false in the functional design is still false here.
# Omit it and at-speed capture reports a violation on a path that cannot be
# sensitised - a false failure that costs debug time and sometimes silicon.
set_false_path -from [get_pins fp_src/Q] -to [get_pins fp_dst/D]
set_multicycle_path 2 -setup -from [get_pins mc_src/Q] -to [get_pins mc_dst/D]
 
# NOTE what is NOT here: a blanket false path over the scan logic. The scan
# muxes and the chain are real silicon carrying real capture-mode paths. Cutting
# them wholesale would make this run pass by not analysing anything.
 
# ---- Boundary-scan I/O ----------------------------------------------------
set_input_delay  1.0 -clock clk_ref [get_ports bscan_in]
set_output_delay 1.0 -clock clk_ref [get_ports bscan_out]

Signoff is the conjunction. Functional and shift and capture-at-speed must each close in their own run. A design clean in one mode says nothing about the others, and functional-clean alone is not test-clean.

The SDC building blocks map onto the modes:

# One file, "covering" all three modes.
set_case_analysis 0 [get_ports test_mode]        ;# functional
set_case_analysis 0 [get_ports scan_enable]
create_clock -name clk_core  -period 2.000  [get_ports CLK]
 
set_case_analysis 1 [get_ports test_mode]        ;# shift
set_case_analysis 1 [get_ports scan_enable]
create_clock -name clk_shift -period 20.000 [get_ports test_clk]
 
set_case_analysis 1 [get_ports test_mode]        ;# capture
set_case_analysis 0 [get_ports scan_enable]
create_generated_clock -name occ_cap -source [get_ports pll_ref] \
    -divide_by 1 [get_pins occ/cap_clk_out]

Warning: set_case_analysis on port 'scan_enable' overrides a previous
         setting (1 -> 0).                                    [SDC-011]
Warning: set_case_analysis on port 'test_mode' overrides a previous
         setting (0 -> 1).                                    [SDC-011]

# 1. After loading constraints, assert the mode is the one intended.
proc assert_mode {expect_tm expect_se} {
  set tm [get_attribute [get_ports test_mode]   case_value]
  set se [get_attribute [get_ports scan_enable] case_value]
  if {$tm != $expect_tm || $expect_se != $se} {
    error "MODE MISMATCH: test_mode=$tm scan_enable=$se, expected \
           $expect_tm/$expect_se"
  }
}
assert_mode 1 1     ;# in the shift run
 
# 2. Fail the flow on case-analysis override warnings rather than printing them.
set_message_severity SDC-011 error

7. Industry Flow — define modes, select, clock, except, close all

The DFT constraint flow: define the modes, select each with case analysis, clock and except it, then close all for test-clean signoff:

7b. Where This Is Specified

• Synopsys Design Constraints (SDC). create_clock, create_generated_clock, set_case_analysis, set_false_path, set_multicycle_path, set_input_delay / set_output_delay, and set_clock_groups. Case analysis is a property of the analysis run: a later set_case_analysis on a port replaces an earlier one rather than describing an alternative scenario.
• IEEE 1149.1-2013 — Standard for Test Access Port and Boundary-Scan Architecture. The boundary-scan pins constrained by the I/O delays in the capture run.
• IEEE 1500-2005. Core test wrappers, which introduce the same class of mode-dependent constraints at core boundaries.
• IEEE 1687-2014 (IJTAG). Reconfigurable instrument networks, whose additional scan configurations each require their own constrained run.

Scan insertion, lock-up latch placement, OCC architecture, and the launch-off-shift versus broadside choice are established engineering practice rather than standardised behaviour; they are implemented by the scan-insertion and ATPG tools and documented per tool.

8. Debugging Session — functional-clean silicon fails scan shift

9. Common Mistakes

• Constraining only the functional mode. DFT adds shift and capture-at-speed modes — each needs its own SDC (12.1).
• Skipping case analysis. Without set_case_analysis, STA sees the wrong topology — it can't tell shift from capture.
• Reusing functional clocks for shift. Shift uses a slow shift clock and needs HOLD checks (12.2) — not the mission clock.
• Not honoring false/multicycle at-speed. They become false at-speed fails (12.4) — carry the exceptions into the at-speed run.
• Calling functional-clean "signoff". Test-clean = all modes clean — an unconstrained mode fails in silicon.

10. Industry Best Practices

• Run multi-mode STA — functional, shift, capture-at-speed — each a separate scenario with its own SDC.
• Use set_case_analysis to select each mode's topology (test_mode / scan_enable).
• Define per-mode clocks — slow shift clock; fast functional/at-speed + OCC-generated pulses.
• Carry functional false-path/multicycle exceptions into the at-speed run; constrain SE (12.3) and boundary-scan I/O (10.x).
• Sign off only when all modes are clean — test-clean, not just functional-clean (12.1).

11. Senior Engineer Thinking

• Beginner: "Functional timing closed — we're signed off."
• Senior: "Functional-clean is one mode. DFT added shift and capture-at-speed — each a separate STA problem. I put the design in each topology with set_case_analysis, give each its own clocks (slow shift clock; fast/OCC pulses), run the right check (hold for shift, setup for capture), and honor false/multicycle at-speed. We're signed off only when all modes are clean — test-clean, not just functional-clean. If a mode won't close, that's DFT debug (Ch13)."

The senior treats signoff as multi-mode and knows an unconstrained test mode is a silicon failure waiting to ship.

12. Silicon Impact

DFT constraints for STA are where the entire timing thread of Chapter 12 becomes actionable and verifiable — the point at which "DFT has its own timing" turns into "STA has proven every test mode is clean." The chapter established that DFT adds real hardware and new modes (12.1), each with its own timing: shift is a HOLD problem and capture is a SETUP problem (12.2), scan-enable must meet setup before the capture edge (12.3), and at-speed launches and captures one functional period apart (12.4). The unavoidable consequence is multi-mode STA: functional, shift, and capture-at-speed are different timing problems, so each must be analyzed in its own run with its own constraints — and the mechanism is SDC. You select each mode's topology with set_case_analysis on test_mode / scan_enable (so STA sees the scan muxes / OCC path and the shift-vs-capture flop configuration); you define per-mode clocks (a slow shift clock; the fast functional/at-speed clock and OCC-generated launch/capture pulses); you add exceptions that honor functional false/multicycle paths in the capture-at-speed run (so they don't become the false at-speed fails of 12.4), plus the SE setup/hold constraint (12.3) and boundary-scan I/O delays (10.x); and you close each mode with its right check — HOLD across adjacent scan cells for shift, SETUP launch-to-capture at the functional period for capture. The closing rule of the chapter is the one that separates a working test program from silent silicon failures: a design is test-clean only when every mode — functional and shift and capture-at-speed — is timing-clean; functional-clean alone is not enough (12.1). A mode you never constrain carries hidden violations — shift hold violations that surface as chain miscompares, at-speed problems and false fails — that pass signoff invisibly and fail in silicon. For the STA engineer, this is the core multi-mode deliverable; for the DFT engineer, it's the validation that the scan/OCC/SE/boundary-scan hardware they built is timing-correct in every mode it's used; for the whole program, it's the bridge from design to manufacturable, testable silicon. And it's exactly where Chapter 13 — DFT Debug begins: when a mode won't close, or silicon fails a test, you take these per-mode constraints and modes and debug them — the SDC of this lesson is both the signoff artifact and the map you debug against.

13. Engineering Checklist

• Ran multi-mode STA — functional, shift, capture-at-speed — each a separate scenario/SDC.
• Selected each mode's topology with set_case_analysis (test_mode / scan_enable).
• Defined per-mode clocks — slow shift clock; fast functional/at-speed + OCC-generated pulses.
• Honored functional false-path/multicycle exceptions at-speed; constrained SE (12.3) and boundary-scan I/O (10.x).
• Signed off only when all modes are clean — test-clean, not just functional-clean (12.1).

14. Try Yourself

1. Explain why functional, shift, and capture-at-speed must be separate STA runs (different clocks/topology/checks).
2. Write representative set_case_analysis for shift (scan_enable=1) vs capture (scan_enable=0) and say what each selects.
3. Give the per-mode clocks: a slow shift clock (create_clock) and OCC launch/capture pulses (create_generated_clock).
4. Show a set_false_path / set_multicycle_path that honors a functional exception in the at-speed run (avoids a false at-speed fail, 12.4).
5. State the signoff rule: all modes clean = test-clean; why functional-clean alone is not enough (12.1).

All SDC here is representative, simplified, and tool-neutral — it illustrates intent, not any one vendor's exact commands. No paid tool is required to reason about the per-mode constraints.

15. Interview Perspective

• Weak: "You write SDC to constrain the design for timing."
• Good: "DFT modes need their own constraints — a shift clock, case analysis for scan-enable, and false paths for at-speed."
• Senior: "DFT adds real hardware and new modes (12.1), each with its own timing — so STA is multi-mode: functional, shift, and capture-at-speed are separate runs, each with its own SDC. I select each mode's topology with set_case_analysis on test_mode / scan_enable, define per-mode clocks (a slow shift clock; the fast/at-speed clock and OCC-generated pulses), add exceptions that honor functional false/multicycle paths in the at-speed run (else false at-speed fails, 12.4), and constrain SE (12.3) and boundary-scan I/O (10.x). Each mode gets its right check — hold for shift, setup for capture. And signoff means all modes clean — test-clean, not just functional-clean; an unconstrained mode fails in silicon (chain miscompare, false at-speed fail). When a mode won't close, that's DFT debug."

16. Interview / Review Questions

17. Key Takeaways

• DFT adds real hardware and new modes (12.1), each with its own timing (12.2–12.4) → STA must analyze each mode separately with the right constraints — multi-mode STA (functional / shift / capture-at-speed).
• set_case_analysis selects each mode's topology (test_mode=1 → scan/OCC path on; scan_enable=1 → shift config, =0 → capture config) so STA sees the right logic.
• Per-mode clocks: a slow shift clock (create_clock) for shift; the fast functional/at-speed clock and OCC-generated launch/capture pulses (create_generated_clock) for capture (12.4).
• Exceptions honor functional false/multicycle paths in the capture-at-speed run (else false at-speed fails, 12.4); constrain SE setup/hold (12.3) and boundary-scan I/O (10.x). Shift checks HOLD; capture checks SETUP at the functional period.
• Signoff: a design is test-clean only when all modes — functional AND shift AND capture-at-speed — are timing-clean; functional-clean alone is not enough (12.1). All SDC here is representative/tool-neutral. A mode that won't close → DFT debug (Chapter 13).

18. Quick Revision

DFT constraints for STA (Ch12 closer). DFT = real hardware + new modes (12.1), each with its own timing (shift=HOLD, capture=SETUP 12.2 ; SE setup 12.3 ; at-speed 12.4) → multi-mode STA: functional / shift / capture-at-speed = SEPARATE runs, each its own SDC. set_case_analysis selects the topology (test_mode=1 scan/OCC on ; scan_enable=1 SHIFT vs =0 CAPTURE). Per-mode clocks: slow shift clock (create_clock) ; fast/at-speed + OCC pulses (create_generated_clock, 12.4). Exceptions: set_false_path/set_multicycle_path honor functional false/multicycle in the at-speed run (else false at-speed fails, 12.4) ; constrain SE (12.3) + boundary-scan I/O (10.x). Checks: shift=HOLD across adjacent cells ; capture=SETUP launch→capture at the functional period. Signoff = ALL modes clean = TEST-CLEAN ; functional-clean alone is NOT enough (12.1). SDC here is REPRESENTATIVE/tool-neutral. A mode not clean → DFT debug (Ch13). Chapter 12 complete.