Scan-Enable Timing & Setup/Hold

Chapter 12 · Section 12.3 · DFT Constraints & Timing

Project thread — the mini-SoC's scan-enable must meet setup to the capture clock at every flop; 12.4 covers the at-speed capture it enables, 12.5 constrains it in STA.

1. Why Should I Learn This?

Scan-enable timing is the #1 cause of intermittent at-speed corruption — and its setup/hold to the capture clock is what you must constrain and close.

• SE selects shift (D=SI) vs capture (D=functional) — must be stable/correct at the clock edge.
• SE 1→0 must settle before the capture edge at every flop — an SE setup requirement to the capture clock.
• Global/high-fanout → skew → a race at-speed (fast capture beats slow SE) → late SE captures SI → corrupt.
• Build SE like a clock (balanced/pipelined, dedicated fast SE); constrain it like data (setup/hold).

2. Real Silicon Story — the SE that arrived late at the corner

A chip's at-speed test corrupted intermittently — specific corner flops captured wrong values, on some dies, some runs. Slow scan passed; the logic was fine. The team suspected marginal logic or a flaky tester.

The cause was scan-enable setup. SE is a global, high-fanout net, and it had been routed as an ordinary signal — so it reached the far/heavily-loaded corner flops late. At slow capture, SE had time to settle everywhere. But at at-speed, the fast capture edge arrived before SE had fallen to 0 at those corner flops — so they were still in shift mode at capture and captured SI (the shift value) instead of the functional response → corruption, exactly at the flops where SE was slowest.

The fix was SE timing discipline: balance/pipeline SE like a clock tree, add a dedicated fast SE for at-speed, and constrain SE's setup to the capture clock in STA so the tool catches the violation. At-speed then passed. Lesson: SE must meet setup before the capture edge at every flop — and because it's global/high-fanout, that's a race at-speed; a late SE captures SI → corrupt, so build SE like a clock and constrain it like data.

3. Factory Perspective — SE timing through each lens

• What the CTS/physical engineer sees: SE as a high-fanout net to balance (like a clock tree), with low skew and a possible dedicated fast SE — a distribution task.
• What the STA/timing engineer sees: SE's setup/hold to the capture clock — a constraint to add and close, especially at-speed.
• What the RTL/DV engineer sees: that SE is timing-critical (not an ordinary control) and that at-speed validity depends on it.
• What management cares about: that at-speed test validity (timing defects, DPPM, 2.3/1.5) depends on SE timing — an intermittent, hard-to-debug failure if SE is left as an ordinary net.

4. Concept — SE setup/hold to the capture clock

What SE does (the timing-relevant role):

• SE selects the flop's data source via the scan mux (3.2): SE=1 → D=SI (shift), SE=0 → D=functional (capture).
• So SE must be stable and at its correct value at the clock edge — like any control steering a mux into a flop.

The critical event — shift → capture:

• SE 1 → 0 must complete and settle to 0 at every flop before the capture edge → SE setup to the capture clock.
• If SE is late (still 1 at a flop when capture fires) → that flop is still in shift mode → captures SI → corrupted (3.4).
• SE hold: SE must also hold its value after the edge (stable through the capture).
• (An SE that changes too early — before the last shift — could break the shift; SE hold w.r.t. the shift clock matters too.)

Why it's a race — global/high-fanout + at-speed:

• SE fans out to every flop → it's global with real skew across the die.
• Slow capture: SE has time to settle → easy. At-speed: the fast capture edge can arrive before SE settles at the far/loaded flops → a race → those flops capture SI (3.4/11.3).

The fixes:

• Balance/pipeline SE — build it like a clock tree (low skew, controlled fanout).
• Dedicated fast SE for at-speed (a faster, lightly-loaded SE for the critical capture).
• Hold shift an extra cycle — give SE time to settle before capture.
• Constrain SE in STA — its setup/hold to the capture clock — so the tool catches violations (12.5).

The dual nature (the key):

• SE is distributed almost like a clock (balanced, low-skew) but timed like a data/control signal (setup/hold to the capture clock). Build it like a clock; constrain it like data.

5. Mental Model — a 'switch tracks' order before a fast train

Scan-enable is like a 'switch the tracks' order that must reach every switch operator on the line before a fast train arrives.

• The order is 'go from siding to main line' (SE 1 → 0, shift → capture). It must reach every operator (every flop) and be acted on (settle) before the train (the capture edge) reaches their switch.
• At a slow train (stuck-at), there's plenty of time — every operator switches before it arrives.
• At a fast train (at-speed), the order must beat the train to the far operators — but if the order is broadcast slowly (SE is a high-fanout, unbalanced net), a far operator hasn't switched yet when the fast train hits their switch — so the train takes the wrong track (the flop captures SI) → derailment (corruption).
• The fix: broadcast the order as fast and evenly as the train timetable (build SE like a clock), give the far operators a priority line (dedicated fast SE), or hold the train one extra stop (an extra shift cycle) so the order lands.

A 'switch tracks' order that must reach every switch before a fast train — build the broadcast like the timetable (a clock), and check every switch flips in time (constrain like data).

6. Working Example — SE setup, and a late-SE corruption

Trace SE setup to the capture clock and the late-SE failure:

# Scan-enable setup to the capture clock - REPRESENTATIVE, SIMPLIFIED, tool-neutral:
  SHIFT:   SE = 1 (held) ; shift clock -> load chains
  SWITCH:  SE 1 -> 0 must SETTLE to 0 at EVERY flop BEFORE the capture edge  (SE SETUP to the capture clock)
  CAPTURE: SE = 0 (settled) ; capture clock -> flop selects FUNCTIONAL D -> valid response
  LATE-SE FAILURE (at-speed):
    SE is global/high-fanout -> reaches a FAR flop LATE ; the FAST at-speed capture edge arrives while SE is still 1 there
    -> that far flop is STILL in shift mode -> its D = SI (shift value) -> it CAPTURES SI, not the functional response
    -> corrupted capture at the far flops -> INTERMITTENT at-speed fails (depends on SE arrival / skew)
  FIX: balance/pipeline SE (like a clock tree) ; dedicated FAST SE ; hold shift an extra cycle ; constrain SE setup in STA
# Slow capture: SE has time to settle -> OK. At-speed: SE-settle is a RACE. Build SE like a CLOCK, constrain like DATA.

The waveform shows SE settling (or arriving late):

7. Industry Flow — build SE like a clock, constrain like data

SE is distributed like a clock and constrained like a data signal to the capture clock:

8. Debugging Session — at-speed corrupts at the corner flops

9. Common Mistakes

• Routing SE as an ordinary net. It's global/high-fanout — build it like a clock tree (balanced, low-skew).
• Not constraining SE in STA. Add its setup/hold to the capture clock — or STA won't flag a late SE (12.5).
• Blaming logic/tester for at-speed corruption. Localized corner corruption + clean slow scan = an SE setup miss.
• Forgetting the dedicated fast SE. At-speed's tight capture may need a faster SE than the general one.
• Ignoring SE hold w.r.t. shift. An SE that changes too early can also break shift.

10. Industry Best Practices

• Distribute SE like a clock — balanced/pipelined, low-skew, dedicated fast SE for at-speed.
• Constrain SE setup/hold to the capture clock in STA (12.5) — verify at every flop, especially at-speed.
• Hold shift an extra cycle if SE can't settle in time.
• Read SE as timing-critical, not an ordinary control (3.4/11.3).
• Diagnose corner at-speed corruption as SE setup before chasing logic/tester.

11. Senior Engineer Thinking

• Beginner: "At-speed corrupts at some flops — the logic there is marginal, or the tester's flaky."
• Senior: "Slow scan passes, corruption is localized to far flops — that's a scan-enable setup miss. SE is global/high-fanout; routed like an ordinary net, it's late at the corner, so the fast capture beats it and those flops capture SI. I build SE like a clock (balance, dedicated fast SE) and constrain its setup to the capture clock in STA. Build like a clock; constrain like data."

The senior reads localized at-speed corruption as an SE setup violation and builds SE like a clock / constrains like data.

12. Silicon Impact

Scan-enable timing is one of the highest-value, most-misdiagnosed topics in DFT timing, because SE is a signal with a dual nature and a failure mode that hides. SE selects the flop's data source (shift vs capture), so it must meet setup before the capture edge (and hold after) at every flop — but it is global and high-fanout, so it carries real skew, and the settle-before-capture requirement becomes a race, acute at-speed where a fast capture clock can beat a slow global SE. When it loses that race, the far/heavily-loaded flops are still in shift mode at capture and capture SI instead of the functional response — producing intermittent at-speed corruption localized to exactly the flops where SE is slowest, while slow scan passes cleanly. That signature is routinely misdiagnosed as marginal logic or a flaky tester, wasting effort — when it is, in fact, an SE setup violation to the capture clock that was never constrained, so STA never flagged it. The remedy captures SE's dual nature: build it like a clock (balanced/pipelined, low-skew, with a dedicated fast SE for at-speed) yet constrain it like a data/control signal (setup/hold to the capture clock in STA, 12.5) — plus hold shift an extra cycle where needed. This makes a silent, intermittent failure into a caught, closed timing check. For the CTS/physical engineer, SE is a clock-tree-like distribution problem; for the STA/DFT engineer, SE is a constraint to add and close; and for the whole flow, at-speed test validity — and thus the timing-defect coverage and DPPM (2.3/1.5) that at-speed underwrites — depends on SE meeting setup. This is the timing counterpart of the SE-settle issue introduced functionally in 3.4/11.3, and it's a core piece of the at-speed capture (12.4) and STA constraints (12.5) that make the Chapter 11 modes timing-close in silicon.

13. Engineering Checklist

• Distributed SE like a clock — balanced/pipelined, low-skew; dedicated fast SE for at-speed.
• Constrained SE setup/hold to the capture clock in STA (12.5) — verified at every flop, at-speed.
• Considered holding shift an extra cycle if SE can't settle in time.
• Treated SE as timing-critical (not an ordinary control).
• Diagnosed corner at-speed corruption as SE setup (clean slow scan) before chasing logic/tester.

14. Try Yourself

1. Explain why SE must meet setup before the capture edge (it selects the flop's data source).
2. Show a late SE at a far flop at an at-speed capture → the flop captures SI → corruption.
3. Explain why slow capture tolerates a late SE but at-speed does not (the settle race).
4. Give the fixes: balance/pipeline SE, dedicated fast SE, hold shift a cycle, constrain SE in STA.
5. State the dual nature: build SE like a clock, constrain it like data — and why.

The SE timing is tool-neutral; distribution is CTS/physical, the constraint is STA (12.5). No paid tool required to reason about SE timing.

15. Interview Perspective

• Weak: "Scan-enable switches between shift and capture."
• Good: "Scan-enable must settle before capture; it's global so it can be late, corrupting the capture."
• Senior: "Scan-enable selects the flop's data source — SI (shift) vs functional (capture) — so it must meet setup before the capture edge at every flop (and hold after). But SE is global/high-fanout, so it has skew, and settle-before-capture is a race — especially at-speed, where a fast capture clock can beat a slow global SE at the far/loaded flops, leaving them in shift mode so they capture SI → corrupt. That's intermittent at-speed corruption localized to the far flops with clean slow scan — almost always an SE setup miss, not marginal logic or a flaky tester. The fix captures SE's dual nature: build it like a clock (balanced/pipelined, low-skew, a dedicated fast SE) yet constrain it like data (setup/hold to the capture clock in STA), and hold shift an extra cycle if needed. Build like a clock; constrain like data."

16. Interview / Review Questions

17. Key Takeaways

• Scan-enable selects the flop's data source — shift (D=SI) vs capture (D=functional) — so it must be stable and correct at the clock edge: meet setup before the capture edge and hold after.
• The critical event is SE 1→0 (shift→capture), which must settle to 0 at every flop before the capture edge — an SE setup requirement to the capture clock.
• SE is global/high-fanout, so skew makes settle-before-capture a race — especially at-speed, where a fast capture clock can beat a slow global SE at the far flops, leaving them in shift mode so they capture SI → corrupted (the #1 cause of intermittent at-speed corruption).
• Fixes: balance/pipeline SE (build it like a clock tree), add a dedicated fast SE for at-speed, hold shift an extra cycle, and constrain SE's setup/hold to the capture clock in STA (12.5).
• The dual nature: SE is distributed like a clock (balanced, low-skew) but timed like a data/control signal (setup/hold to the capture clock) — build it like a clock, constrain it like data; localized at-speed corruption with clean slow scan is almost always an SE setup miss, not logic/tester. Next: 12.4 — at-speed test & fast capture.

18. Quick Revision

Scan-enable timing & setup/hold. SE selects shift (D=SI) vs capture (D=functional) → must meet SETUP before the capture edge + HOLD after. Critical event: SE 1→0 must SETTLE at EVERY flop BEFORE the capture edge (SE setup to the capture clock). SE is GLOBAL/high-fanout → SKEW → a RACE at-speed (fast capture beats slow SE) → a LATE SE leaves a far flop in shift mode → it captures SI → CORRUPT (the #1 intermittent at-speed bug; localized to far flops, clean slow scan). Fixes: balance/pipeline SE (build like a CLOCK), dedicated FAST SE, hold shift an extra cycle, CONSTRAIN SE setup/hold to the capture clock in STA (12.5). Dual nature: build like a clock, constrain like data. Not marginal logic / flaky tester. Next: 12.4 — at-speed test & fast capture.