Working Example: MBIST on a Memory Block

Chapter 8 · Section 8.6 · Memory BIST (MBIST) — chapter capstone

Project thread — the mini-SoC memory (the 7.5 X-source) is wrapped, MBIST-tested (March C-), repaired (BISR), and bypassed in scan — closing the 7.5 loop and readying both domains for signoff.

1. Why Should I Learn This?

This is Chapters 8 (and 7.5) working together — the concrete moment a memory becomes tested, repaired, and out of scan's way.

• Wrap the memory (functional/BIST + scan-bypass) → fixes the 7.5 X-source.
• Run March C- (8.3) at-speed; detect a fault; capture the failing address (8.4).
• Repair via BISR (8.5): allocate a spare → apply → re-test → good die.
• Result: memory tested + repaired, logic compression clean — both domains covered.

2. Real Silicon Story — the memory that finally behaved

The mini-SoC's memory had been two problems at once: it corrupted scan compression as an X-source (7.5), and it was untested (scan can't test an array, 8.1) — so it was both hurting logic coverage and hiding its own defects.

MBIST + BISR + a proper wrapper solved all of it in one integration. The wrapper put the memory in BIST mode for its own test and bypassed/initialized it in scan — so it stopped feeding X into the compactor and logic compression coverage recovered (closing 7.5). The MBIST controller ran March C- at-speed and caught a coupling fault the old 'simple test' would have missed (8.2), capturing the failing address. BISR allocated a spare row, applied the repair, and the memory passed re-test — a good die that would otherwise have been scrapped (yield, 1.2).

Lesson: a single, well-integrated MBIST + BISR + wrapper turns a memory from a coverage liability and an untested risk into a tested, repaired, scan-friendly block — each defect domain (logic vs memory) handled by the right tool.

3. Factory Perspective — the integrated memory through each lens

• What the test engineer sees: an MBIST run (March C-, at-speed) with a go/no-go + failing address, a BISR repair, a re-test pass, and clean logic compression (memory bypassed in scan) — all via JTAG (Ch10).
• What the yield engineer sees: a repaired die (BISR) that would've been scrapped — yield recovered (1.2) — plus the memory's defects now caught (fewer escapes).
• What the RTL/DV / memory engineer sees: the wrapper integration done right — functional/BIST + scan-bypass — resolving the 7.5 X-source on their block.
• What management cares about: that one integration delivers memory coverage + yield (repair) + clean logic compression — a big DPPM (1.5) + yield (1.2) + test-cost (1.4) win.

4. Concept — the end-to-end flow on the memory

Step 1 — Wrap the memory (8.4):

• Insert the MBIST wrapper/controller. The wrapper selects: functional (mission), BIST (self-test), and scan-bypass (memory outputs initialized/known in scan → no X at the compactor — the 7.5 fix).

Step 2 — Run March C- at-speed (8.3):

• The control FSM sequences March C-; the address generator sweeps ⇑/⇓; the data generator supplies 0/1 + backgrounds. The memory is written/read at-speed.

Step 3 — Detect + capture (8.4):

• The comparator checks each read vs expected → go/no-go; on a mismatch (e.g. a stuck-at or coupling fault), it captures the failing address/bits.

Step 4 — Repair via BISR (8.5):

• BIRA allocates a spare row/column to cover the failing address; the repair is applied (hard e-fuse / soft register); the memory is re-tested → PASS → good die (or repair-impossible if fails exceed spares → reject).

Step 5 — The result (closing 7.5):

• The memory is now tested (MBIST — its own coverage), repaired (yield), and bypassed in scan (clean logic compression). Logic → scan/ATPG/compression; memory → MBIST — both feed signoff (6.5)/DPPM (1.5).

5. Mental Model — a self-cleaning, self-repairing library wing

The finished memory is like a library wing that inspects, repairs, and stays out of the main audit's way — by itself.

• A robot librarian (MBIST controller) runs the inspection walk (March C-) at full pace, checks every shelf, and writes down which shelf failed (failing address).
• A facilities system (BISR) reads that note, reassigns the broken shelf's contents to a spare-row shelf (allocate + apply), and the wing re-passes inspection — a broken shelf no longer condemns the wing (yield saved).
• A switchable door (wrapper) lets the wing run normally, hand over to the robot (BIST), or seal itself off during the building-wide audit (scan) so its half-shelved chaos doesn't confuse the auditors (no X into the compactor — the 7.5 fix).
• You manage the whole thing from the front desk (JTAG): 'run inspection,' 'which shelf failed,' 'apply the repair.'

One integration makes the wing self-testing, self-repairing, and audit-friendly — the memory's whole arc in a single wrapper.

6. Working Example — the MBIST run and repair

The end-to-end run on the mini-SoC memory:

# MBIST + BISR run on the mini-SoC memory - REPRESENTATIVE, SIMPLIFIED, tool-neutral:
  1) WRAP: MBIST wrapper -> functional / BIST / SCAN-BYPASS (in scan, memory outputs = known -> NO X, fixes 7.5)
  2) RUN (bist_en=1): control FSM runs MARCH C- (8.3) at-speed:
       ⇕(w0); ⇑(r0,w1); ⇑(r1,w0); ⇓(r0,w1); ⇓(r1,w0); ⇕(r0)   (addr gen up/down; data gen 0/1 + backgrounds)
  3) DETECT: on ⇑(r1,...) the comparator finds a MISMATCH at ADDRESS 0x089 (a coupling fault, 8.2)
       -> go/nogo = FAIL ; capture FAILING ADDRESS = 0x089 (8.4)
  4) REPAIR (BISR, 8.5): BIRA allocates SPARE ROW #1 -> covers row of 0x089 ; APPLY (blow e-fuse / load register)
  5) RE-TEST: re-run March C- -> PASS -> GOOD, shippable die (yield recovered, 1.2)
  RESULT: memory TESTED (MBIST) + REPAIRED (BISR) + BYPASSED in scan (clean logic compression) -> both -> signoff (6.5)

# Closing the 7.5 loop - REPRESENTATIVE:
  BEFORE (7.5): memory NON-scan-bypassed -> X floods the compactor -> heavy masking -> logic coverage 95.8%
  AFTER (8.6):  wrapper BYPASSES/INITS memory in scan -> NO X into compactor -> masking shrinks -> logic coverage 99.3%
                AND memory tested by MBIST (its own coverage) + repaired (yield)
  -> each defect domain the RIGHT tool: logic -> scan/compression (Ch3-7) ; memory -> MBIST (Ch8).

The waveform shows the March write/read detecting the fault at the failing address:

7. Industry Flow — the memory joins signoff, both domains covered

The integrated memory feeds signoff alongside logic, and sets up in-system BIST:

8. Debugging Session — logic coverage still hurt after MBIST

9. Common Mistakes

• Adding the controller but not the scan-bypass. Test the memory and bypass it in scan — both jobs (7.5/8.4).
• Go/no-go without failing-address capture. For a repairable memory, capture the address for BISR (8.4/8.5).
• Skipping re-test after repair. A repaired memory must still pass (DPPM, 1.5).
• Using a too-weak March. March C- (or stronger) for coupling/retention (8.2/8.3) — not a simple test.
• Running MBIST slowly. It must be at-speed (timing/retention, 8.2/8.3).

10. Industry Best Practices

• Wrap for functional/BIST and scan-bypass — test the memory and resolve the 7.5 X-source.
• Run a March matched to the fault classes (8.2/8.3), at-speed, with failing-address capture (8.4).
• Repair via BISR + re-test (8.5) — recover yield (1.2) without compromising quality (1.5).
• Report memory coverage with logic coverage toward the DPPM target (6.5).
• Enable JTAG access (Ch10) for run/diagnosis/repair — and consider in-field/power-on BIST (Ch9).

11. Senior Engineer Thinking

• Beginner: "I added MBIST but logic coverage is still low — MBIST doesn't work."
• Senior: "MBIST does two jobs: test the memory (controller — working) and keep it out of scan's way (wrapper scan-bypass — check this!). Your logic loss is the wrapper, not MBIST — the memory's still an X-source (7.5). I configure the scan-bypass, re-baseline, and logic compression recovers. Meanwhile MBIST tested and BISR-repaired the memory — both domains covered."

The senior separates the two jobs (test the memory vs bypass it in scan) and completes both.

12. Silicon Impact

This capstone is where the whole memory-test arc pays off on a real block — and where the 7.5 loop finally closes. In one integration, the mini-SoC memory goes from a double liability (an untested array and an X-source corrupting scan compression) to a triple win: it is tested by MBIST (its own coverage — catching coupling/retention/decoder faults scan never could, 8.2), repaired by BISR (recovering yield a scrap would waste, 1.2/8.5), and bypassed in scan (removing the X at the compactor so logic compression runs clean, 7.5). The demonstration makes the chapter's thesis concrete: each defect domain needs the right tool — logic → scan/ATPG/compression (Ch3–7); memory → MBIST (Ch8) — and a well-designed wrapper lets both coexist, so both memory and logic coverage feed signoff (6.5) and the DPPM commitment (1.5). The debugging session drives home the integration subtlety that trips real teams: MBIST has two jobs — test the memory (controller) and keep it out of scan's way (wrapper scan-bypass) — and doing only the first leaves the 7.5 X-source intact, so a persistent logic-compression loss after MBIST insertion is a wrapper problem, not an MBIST failure. Finally, because MBIST is on-chip, this same hardware enables in-field / power-on memory test — the bridge to Chapter 9 (Logic BIST), which brings self-test to logic for in-system operation, and Chapter 10 (boundary scan / JTAG), the access mechanism that starts BIST and reads results. For the RTL/DV / memory engineer, the lasting lesson is that memory test is an integration you own — wrap, MBIST, repair, bypass-in-scan — and getting it right delivers coverage, yield, and clean logic compression all at once, exactly the multi-objective win a memory-heavy SoC needs.

13. Engineering Checklist

• Wrapped the memory: functional / BIST / scan-bypass (fixes the 7.5 X-source).
• Ran a March matched to fault classes (C-/SS, 8.2/8.3) at-speed, with failing-address capture (8.4).
• Repaired via BISR (spare allocation + apply) and re-tested (yield 1.2; DPPM 1.5) (8.5).
• Verified logic compression coverage recovered (memory bypassed → no X, 7.5).
• Reported memory + logic coverage toward the DPPM target (6.5); enabled JTAG access (Ch10).

14. Try Yourself

1. Draw the memory with MBIST controller + wrapper + BISR; label functional / BIST / scan-bypass.
2. Run March C- (8.3); detect a coupling fault at an address; capture it (8.4).
3. Repair via BISR: allocate a spare row, apply, re-test → pass (8.5).
4. Show the scan-bypass removing the X at the compactor → logic coverage recovers (7.5).
5. Confirm both domains (memory via MBIST, logic via scan) feed signoff (6.5).

The flow is tool-neutral; MBIST/BISR are memory/DFT IP. A free simulator can model the March/compare. No paid tool required.

15. Interview Perspective

• Weak: "You put MBIST on the memory to test it."
• Good: "Wrap the memory, run a March test with the controller, detect faults, and repair with BISR."
• Senior: "I run the whole flow. Wrap the memory (functional / BIST / scan-bypass — the scan-bypass fixes the 7.5 X-source). Run March C- (8.3) at-speed via the controller; the comparator detects a fault (say a coupling fault) and captures the failing address (8.4). BISR allocates a spare row, applies the repair, and re-test passes → a good die (yield, 1.2). The result: the memory is tested (MBIST), repaired (BISR), and bypassed in scan (clean logic compression) — both domains covered, feeding signoff (6.5). A subtle point: MBIST insertion has two jobs — test the memory and bypass it in scan — so if logic coverage is still low after MBIST, the wrapper's scan-bypass wasn't configured, not an MBIST failure."

16. Interview / Review Questions

17. Key Takeaways

• The full MBIST flow on the mini-SoC memory: wrap it (functional / BIST / scan-bypass), run March C- at-speed (8.3), detect a fault and capture the failing address (8.4), repair via BISR (allocate a spare → apply → re-test → good die, 8.5).
• The result is a triple win: the memory is (a) tested by MBIST (its own coverage — coupling/retention/decoder), (b) repaired (yield recovered, 1.2), and (c) bypassed in scan (no X at the compactor → logic compression runs clean, closing 7.5).
• Each defect domain gets the right tool: logic → scan/ATPG/compression (Ch3–7); memory → MBIST (Ch8) — and both feed signoff (6.5) and the DPPM commitment (1.5).
• MBIST insertion has two distinct jobs — test the memory (controller) and bypass it in scan (wrapper) — so a persistent logic-compression loss after MBIST is a wrapper scan-bypass problem, not an MBIST failure.
• Because MBIST is on-chip, the same hardware enables in-field/power-on memory test — bridging to Chapter 9 (Logic BIST — self-test for logic, in-system) and Chapter 10 (boundary scan / JTAG access). Next: Chapter 9 — Logic BIST (LBIST).

18. Quick Revision

MBIST on a memory block (Ch8 capstone). Full flow on the mini-SoC memory (the 7.5 X-source): WRAP (functional / BIST / SCAN-BYPASS) → RUN March C- at-speed via the controller (8.3) → DETECT a fault (e.g. coupling at 0x089) + capture failing address (8.4) → BISR repair (allocate spare row → apply → re-test → good die, 8.5). Triple win: memory TESTED (MBIST) + REPAIRED (yield, 1.2) + BYPASSED in scan (no X → logic compression clean, fixes 7.5). Each domain the RIGHT tool: logic → scan (Ch3-7); memory → MBIST (Ch8) → both feed signoff (6.5)/DPPM (1.5). MBIST = TWO jobs (test the memory AND bypass in scan) → persistent logic loss = wrapper scan-bypass missing, not MBIST failure. On-chip → in-field/power-on (→ Ch9 LBIST / Ch10 JTAG). Next: Chapter 9 — Logic BIST (LBIST).