DFT · Chapter 8 · Memory BIST (MBIST)
Redundancy & Built-In Self-Repair (BISR)
Large memories ship with spare rows and columns so a defective cell, row, or column can be repaired by swapping in a spare, turning a die that would be scrapped for one bad cell into a good part. Built-in self-repair automates this on-chip: MBIST detects the failing addresses and repair logic remaps them to spares. It runs in three phases. Detect finds the failing addresses with MBIST. Analyze and allocate computes which spare rows or columns cover the failures, which on-chip is built-in redundancy analysis and is non-trivial with a limited set of spares. Apply remaps the addresses. Repair is either hard, using e-fuses blown permanently at test, or soft, using registers re-applied at each power-on. A few spares recover many dies, and when failures exceed the spares the part is genuinely repair-impossible.
Intermediate13 min readDFTBISRRedundancyRepairYield
Chapter 8 · Section 8.5 · Memory BIST (MBIST)
Project thread — the mini-SoC memory, detected faulty by MBIST (8.3/8.4), is repaired here via BISR; 8.6 runs detect→repair end-to-end.
1. Why Should I Learn This?
BISR is why large memories are economically viable — it recovers yield by repairing defects instead of scrapping dies.
- Memories ship with spare rows/columns (redundancy); a defective row/column is swapped for a spare.
- BISR phases: detect (MBIST) → analyze/allocate (BIRA) → apply (remap).
- Hard repair (e-fuse/laser, permanent) vs soft repair (registers, re-applied each power-on).
- A few spares recover many dies (yield, 1.2); too many fails for the spares = repair-impossible (a real reject).
2. Real Silicon Story — the spares that saved a lot
A memory-heavy SoC had healthy logic yield but was failing a large fraction of dies on a single memory — each with just one or two bad cells in a huge array. Every such die was being scrapped, and the yield hit was severe.
The array had spare rows/columns — but the flow wasn't using them: there was no BISR, so a die with one bad row was thrown away exactly like a die with a catastrophic failure. The redundancy was dead weight.
Enabling BISR transformed the numbers. MBIST detected the failing addresses (8.4), BIRA computed a repair solution (which spare row/column covers each failure), and the repair was applied (fuses / soft-repair registers remapping the bad addresses to spares). Most of the 'failing' dies became good, shippable parts — the yield recovered dramatically, from a few spare rows/columns. The only true rejects were the rare dies with more failures than spares (repair-impossible). Lesson: in large memories, some defects are certain — redundancy + BISR recovers the yield that scrapping would waste, and a few spares save many dies (1.2).
3. Factory Perspective — BISR through each lens
- What the yield engineer sees: the big lever — repair recovers dies that would be scrapped; the repair rate and repair-impossible rate are key yield metrics (1.2).
- What the test engineer sees: the detect → allocate → apply flow (via MBIST/JTAG), the fuse map / repair solution, and that the repaired part must be re-tested.
- What the RTL/DV / memory engineer sees: that the memory needs spares + BISR/BIRA + fuses designed in — an architecture decision — and a diagnosis-capable MBIST (8.4) to feed it.
- What management cares about: that a small redundancy area yields a large yield recovery (1.2) — a direct cost/margin win on memory-heavy parts — while repaired parts still meet DPPM (1.5).
4. Concept — spares, the three phases, and repair types
Redundancy (spare rows/columns):
- The array includes extra (spare) rows and/or columns beyond the addressable capacity.
- A defective row/column (or the cell in it) can be replaced by remapping its address to a spare.
BISR — the three phases:
- Detect (MBIST, 8.3/8.4): run the March test; the comparator captures the failing addresses.
- Analyze / allocate (BIRA on-chip): compute a repair solution — which spares cover the failing addresses (redundancy allocation). It's a combinatorial problem: cover a must-repair set with limited spares (row spares fix whole rows, column spares fix whole columns), ideally optimally. If failures exceed the spares → repair-impossible (a genuine reject).
- Apply: remap the failing addresses to the allocated spares (via fuses or repair registers).
Hard vs soft repair:
- Hard repair: e-fuse / laser — permanent; the repair is blown at test and is non-volatile.
- Soft repair: registers — volatile; the repair solution is stored (e.g. in fuses/ROM) and re-applied at each power-on (a boot-time BISR loads the registers).
Why redundancy + repair (the economics):
- Memory arrays are enormous (millions of cells) → some defects are statistically certain even at good defect density.
- Without repair, one bad cell scraps the whole die. With redundancy + BISR, a few spares recover many dies → large yield recovery (1.2) for small area.
Quality note:
- A repaired part must still pass its test (re-run/verify after repair) — repair recovers yield, it doesn't excuse quality (DPPM, 1.5).
5. Mental Model — a stadium with spare seats
Redundancy and BISR are like a stadium that sells N seats but builds a few spare rows.
- If a seat (cell) turns out to be broken, you don't condemn the whole stadium (scrap the die) — you reassign that ticket to a spare-row seat (remap to a spare). The fan never notices — their address just points to a good seat.
- The usher (MBIST) finds the broken seats (failing addresses); the seating manager (BIRA) decides which spare seats to reassign (allocation) — and if too many seats are broken for the spares available, the game can't be seated (repair-impossible → reject).
- Reassignment can be printed permanently on the tickets (hard repair / e-fuse) or loaded fresh each game day from a list (soft repair / registers re-applied at power-on).
- Because a big stadium is certain to have some broken seats, building a few spare rows lets you still sell out — a few spares recover a lot of revenue (yield).
A few spare rows turn 'condemn the stadium' into 'reassign a ticket' — that's redundancy + BISR.
6. Working Example — detect, allocate, apply
Work the mini-SoC memory's repair:
# BISR on the mini-SoC memory - REPRESENTATIVE, SIMPLIFIED, tool-neutral:
Memory: 1M cells, addressable, + 2 spare ROWS + 2 spare COLUMNS (redundancy)
Step 1 DETECT (MBIST, 8.3/8.4): March C- fails -> comparator captures FAILING ADDRESSES:
failing cells cluster in ROW 137 (a bad row) and one isolated cell at (row 900, col 12)
Step 2 ANALYZE/ALLOCATE (BIRA): allocate SPARE ROW #1 -> covers all of row 137 ; SPARE COLUMN #1 -> covers col 12
(must-repair set covered by 1 spare row + 1 spare column, within the 2+2 available -> REPAIRABLE)
Step 3 APPLY: remap row 137 -> spare row #1 ; col 12 -> spare col #1
HARD: blow e-fuses (permanent) ; or SOFT: store solution -> load repair registers each power-on
RE-TEST: re-run MBIST on the repaired memory -> PASS -> a GOOD, shippable die (yield recovered, 1.2)
# Repair-impossible case: if 5 rows failed but only 2 spare rows exist -> can't cover -> genuine REJECT (not a BISR bug).7. Industry Flow — detect → allocate → apply → re-test
BISR is a self-contained repair loop feeding yield:
8. Debugging Session — repairable memories being scrapped
A large fraction of dies fail on one memory with just one or two bad cells and are all scrapped, hurting yield; the array has spare rows/columns but no BISR (or a go/no-go MBIST that can't localize), so repairable memories are thrown away -- the fix is redundancy + BISR (detect/allocate/apply) with a diagnosis-capable MBIST, while a genuine repair-impossible case (fails exceed spares) is a real reject
A FEW SPARES + BISR RECOVER YIELD — SCRAPPING REPAIRABLE MEMORIES WASTES ITA large fraction of dies fail on one memory — each with just one or two bad cells in a huge array — and all are scrapped. Yield is badly hurt (1.2), even though logic yield is fine.
The array has (or could have) spare rows/columns, but there's no working repair path — no BISR, or a go/no-go MBIST that can't localize the failure — so repairable memories with a single bad cell are thrown away exactly like catastrophic failures. Two failure modes lead here: (1) No redundancy/BISR — the memory has no spares (or has spares but no BISR to use them), so any failing cell scraps the die; the redundancy is dead weight or absent. (2) No diagnosis — the MBIST comparator is go/no-go only (8.4), so even with spares and BISR logic, there's no failing-address data to allocate a repair (BIRA needs to know which rows/columns failed). In both cases, the statistically-certain handful of defects in a huge array turns into a scrapped die — which is exactly what redundancy exists to prevent: for large memories, some defects are certain, so a design without repair guarantees a heavy yield loss. (Note: a genuinely repair-impossible die — more failures than spares — is a real reject, not this bug; that's the redundancy working within its limits.)
Provide redundancy (spare rows/columns) plus BISR — detect, allocate, apply — with a diagnosis-capable MBIST, and repairable memories become good parts. Ensure the memory has spare rows/columns, a diagnosis-capable MBIST comparator (8.4) that captures failing addresses, and BISR/BIRA to allocate spares and apply the repair (hard e-fuse or soft register). Then the detect → allocate → apply → re-test loop turns a die with one bad row into a shippable part — recovering yield (1.2) from a small spare area. Track the repair rate and the repair-impossible rate; a die whose failures exceed the spares is a legitimate reject (accept it — the redundancy did its job within its capacity). The principle to lock in: large memories have statistically-certain defects, so they ship with spare rows/columns (redundancy), and built-in self-repair recovers yield by using MBIST to detect the failing addresses, built-in redundancy analysis to allocate spares that cover them (or declare repair-impossible when failures exceed spares), and hard (e-fuse, permanent) or soft (register, re-applied each power-on) repair to remap the failing addresses to spares — so scrapping a memory with one or two bad cells wastes yield the redundancy could recover; the fix is redundancy plus BISR fed by a diagnosis-capable MBIST, and the repaired part is re-tested so repair recovers yield without compromising quality. (The MBIST that feeds it is 8.3/8.4; yield is 1.2; DPPM is 1.5; the worked detect→repair example is 8.6.)
9. Common Mistakes
- Scrapping repairable memories. With redundancy + BISR, a bad row is remapped, not thrown away (yield, 1.2).
- Go/no-go MBIST with redundancy. Repair needs failing addresses — use a diagnosis-capable comparator (8.4).
- Forgetting to re-test after repair. A repaired part must still pass (DPPM, 1.5) — repair isn't a quality excuse.
- Treating repair-impossible as a bug. More fails than spares is a genuine reject — redundancy has limits.
- Ignoring soft-repair boot. Soft repair must be re-applied each power-on (load registers) — design the boot flow.
10. Industry Best Practices
- Design in spare rows/columns + BISR/BIRA for large memories — recover yield (1.2).
- Use a diagnosis-capable MBIST (failing-address capture, 8.4) to feed BIRA.
- Choose hard vs soft repair deliberately (permanent e-fuse vs boot-time register).
- Re-test repaired memories — repair recovers yield, not quality (DPPM, 1.5).
- Track repair rate + repair-impossible rate as yield metrics; size spares to the defect statistics.
11. Senior Engineer Thinking
- Beginner: "The memory failed — scrap the die."
- Senior: "Is it repairable? A huge array is certain to have a few defects — that's why we have spare rows/columns. MBIST captured the failing addresses, BIRA allocates a spare to cover them, and we apply the repair (e-fuse or register). One bad row → remap to a spare → a good die. Only too many fails for the spares is a real reject. A few spares recover many dies."
The senior repairs repairable memories with redundancy + BISR — scrapping them wastes recoverable yield.
12. Silicon Impact
Redundancy and BISR are why large embedded (and standalone) memories are economically viable at all — because at the scale of millions of cells, some defects are statistically certain, so a memory without repair would suffer a guaranteed, heavy yield loss (1.2), scrapping otherwise-good dies for one bad cell. Redundancy (spare rows/columns) plus BISR turns that certainty into a manageable, recoverable event: MBIST detects the failing addresses, BIRA allocates spares to cover them, and hard (e-fuse) or soft (register) repair remaps the bad addresses — so a few spares recover many dies, a large yield return on a small area investment. This is the payoff that justifies much of the MBIST investment (8.1–8.4): the diagnosis-capable comparator (8.4) exists precisely so BISR has the failing-address data it needs — without it, redundancy is dead weight and repairable memories are scrapped (the story). Two boundaries keep the picture honest: a die with more failures than spares is genuinely repair-impossible — a real reject, the redundancy working within its capacity, not a bug; and a repaired part must still pass re-test, because repair recovers yield, not quality — the DPPM commitment (1.5) applies to the repaired device. For the DFT/memory engineer, this makes redundancy + BISR/BIRA + a diagnosis-capable MBIST an architectural must for large memories, and the repair rate a first-class yield/cost lever — the difference between a profitable memory-heavy part and one that bleeds yield. It's how the mini-SoC memory, detected faulty in 8.3/8.4, becomes a repaired, shippable part in 8.6 — completing memory test's full arc from detect to repair.
13. Engineering Checklist
- Designed in spare rows/columns + BISR/BIRA for large memories (yield, 1.2).
- Used a diagnosis-capable MBIST (failing-address capture, 8.4) to feed BIRA.
- Ran detect → allocate → apply — chose hard (e-fuse) vs soft (register, per power-on) repair.
- Re-tested repaired memories (DPPM, 1.5); handled repair-impossible as a genuine reject.
- Tracked repair rate / repair-impossible rate; sized spares to the defect statistics.
14. Try Yourself
- Given a memory with 2 spare rows + 2 spare columns, and failures in row 137 and cell (900,12), allocate spares (BIRA).
- Apply the repair (remap) — describe hard (e-fuse) vs soft (register per power-on).
- Re-test the repaired memory; confirm it must pass (DPPM, 1.5).
- Construct a repair-impossible case (5 failing rows, 2 spare rows) — a genuine reject.
- Estimate the yield recovery from a few spares on a large array with statistically-certain defects (1.2).
The flow is tool-neutral; BIRA/BISR are in memory/DFT IP. No paid tool required to reason about repair.
15. Interview Perspective
- Weak: "Memories have spare cells to fix defects."
- Good: "Spare rows/columns replace defective ones; MBIST finds the failures and repair logic remaps them."
- Senior: "Large memories ship with spare rows/columns (redundancy) because some defects are statistically certain at that scale. BISR recovers yield in three phases: MBIST detects the failing addresses (needs a diagnosis-capable comparator, 8.4); BIRA allocates spares to cover them (redundancy allocation — or repair-impossible if failures exceed spares); and apply remaps the addresses — hard (e-fuse, permanent) or soft (registers, re-applied each power-on). A die with one bad row becomes a good part — a few spares recover many dies (yield, 1.2). The repaired part is re-tested (repair recovers yield, not quality, DPPM 1.5), and too many fails for the spares is a genuine reject, not a bug."
16. Interview / Review Questions
17. Key Takeaways
- Large memories ship with spare rows/columns (redundancy) because at that scale some defects are statistically certain — so a defective row/column is repaired by swapping in a spare instead of scrapping the die.
- Built-in self-repair (BISR) automates this on-chip in three phases: detect (MBIST captures failing addresses, 8.4) → analyze/allocate (BIRA decides which spares cover the failures — or declares repair-impossible) → apply (remap the addresses).
- Repair is hard (e-fuse/laser — permanent, blown at test) or soft (registers — volatile, re-applied at each power-on from stored data).
- A few spares recover many dies — a large yield recovery (1.2) for small area — and the repaired part must still be re-tested (repair recovers yield, not quality; DPPM, 1.5).
- Scrapping repairable memories wastes recoverable yield — the fix is redundancy + BISR fed by a diagnosis-capable MBIST (8.4); a die with more failures than spares is a genuine repair-impossible reject, not a bug. Next: 8.6 — a working example: MBIST on a memory block.
18. Quick Revision
Redundancy & BISR. Large memories ship with SPARE rows/columns (redundancy) because at scale some defects are CERTAIN → repair instead of scrap (yield, 1.2). BISR = 3 phases: DETECT (MBIST captures FAILING ADDRESSES — needs diagnosis-capable comparator, 8.4) → ANALYZE/ALLOCATE (BIRA: which spares cover the failures — or repair-impossible if fails > spares) → APPLY (remap addresses). HARD repair = e-fuse/laser (permanent, blown at test); SOFT = registers (volatile, re-applied EACH power-on). A few spares recover MANY dies. Re-test repaired part (repair recovers yield NOT quality, DPPM 1.5). Repair-impossible (fails > spares) = genuine reject, not a bug. Next: 8.6 — MBIST on a memory block.