All SystemVerilog labs
SystemVerilog Labs
Lab 33of 60
SystemVerilog RTL Foundations6
Strong Typing & Data Modeling6
Parameters, Packages & Reuse5
Interfaces & Modports5
Assertions & Temporal Reasoning7
Testbench Architecture5
OOP Verification Foundations6
Concurrency & Communication5
Constrained Random6
Functional Coverage5
Integrated Verification Projects4
Testbench ArchitecturePublished
Reference Models & Independent Oracles
Write a checker that computes the expected result a different way from the DUT, and see why an oracle that mirrors the design agrees with its bugs.
Advanced~55 minSelf-checking testbench2 challenges
Concepts covered
- Reference model
- Oracle independence
- Golden comparison
This lab is part of SystemVerilog Labs
Unlock the complete lab — language semantics, hardware meaning, complete SystemVerilog source, a self-checking testbench, compiler-diagnostic evidence, debugging walkthroughs and challenges — with the SystemVerilog Labs package.
- Language semantics & hardware meaning
- Complete, runnable SystemVerilog
- Self-checking testbench
- Compiler-diagnostic evidence
- Debugging walkthroughs
- 2 progressive challenges