All SystemVerilog labs
SystemVerilog Labs
Lab 59of 60
SystemVerilog RTL Foundations6
Strong Typing & Data Modeling6
Parameters, Packages & Reuse5
Interfaces & Modports5
Assertions & Temporal Reasoning7
Testbench Architecture5
OOP Verification Foundations6
Concurrency & Communication5
Constrained Random6
Functional Coverage5
Integrated Verification Projects4
Integrated Verification ProjectsPublished
Project — APB-Style Peripheral Verification
Build a reusable bus agent for a simple register-mapped peripheral: modport-enforced connections, protocol assertions for the setup/access phases, a register scoreboard and a coverage model over the address map.
Advanced~180 minSelf-checking testbench4 challenges
Concepts covered
- Bus agent
- Protocol assertions
- Register scoreboard
This lab is part of SystemVerilog Labs
Unlock the complete lab — language semantics, hardware meaning, complete SystemVerilog source, a self-checking testbench, compiler-diagnostic evidence, debugging walkthroughs and challenges — with the SystemVerilog Labs package.
- Language semantics & hardware meaning
- Complete, runnable SystemVerilog
- Self-checking testbench
- Compiler-diagnostic evidence
- Debugging walkthroughs
- 4 progressive challenges