All SystemVerilog labs
SystemVerilog Labs
Lab 14of 60
SystemVerilog RTL Foundations6
Strong Typing & Data Modeling6
Parameters, Packages & Reuse5
Interfaces & Modports5
Assertions & Temporal Reasoning7
Testbench Architecture5
OOP Verification Foundations6
Concurrency & Communication5
Constrained Random6
Functional Coverage5
Integrated Verification Projects4
Parameters, Packages & ReusePublished
Packages, Scope & Import Discipline
Move shared types and constants into a package, then compare wildcard import against explicit import by deliberately creating a name collision and resolving it.
Intermediate~40 minSelf-checking testbench1 challenge
Concepts covered
- package/endpackage
- import
- Scope resolution
This lab is part of SystemVerilog Labs
Unlock the complete lab — language semantics, hardware meaning, complete SystemVerilog source, a self-checking testbench, compiler-diagnostic evidence, debugging walkthroughs and challenges — with the SystemVerilog Labs package.
- Language semantics & hardware meaning
- Complete, runnable SystemVerilog
- Self-checking testbench
- Compiler-diagnostic evidence
- Debugging walkthroughs
- 1 progressive challenge