AMBA AXI · Module 4

Write Ordering & WLAST

How AXI ties the write channels together — WLAST as the data-phase terminator, AW↔W ordering, and the AXI3→AXI4 WID change that removed write-data interleaving.

The three write channels are decoupled — but a write is still one transaction, so something must tie AW, W, and B back together. Two mechanisms do it: WLAST, which terminates the data phase and tells the subordinate where one write's data ends, and the ordering rule, which pairs each W burst to its AW even though the channels run independently. This chapter details WLAST timing, how AW and W relate in time (independent, but paired by order), and the AXI3→AXI4 WID change that removed write-data interleaving — a favorite interview topic and a real bridge headache. It builds on the AW/W/B channels (4.1–4.3); the response codes are next.

1. WLAST — The Data-Phase Terminator

WLAST answers a question the W channel must answer for every burst: where does this write's data end? Because the channels are decoupled and (in AXI4) carry no per-beat ID, the subordinate can't know the burst length from the W channel alone — so the manager asserts WLAST on the final beat to mark the boundary.

WLAST has three jobs, and all three depend on it being on the right beat:

It ends the data phase. The subordinate now has all the write data and may proceed to respond.
It gates B. Per the B-after-W ordering (Module 3.5), BVALID may assert only after the WLAST beat is accepted.
It must match AWLEN. WLAST must land on beat number AWLEN+1 — the count declared on AW. If it lands early or late, the subordinate and the AW disagree on the burst length, malforming the transaction.

So WLAST is the W channel's self-description of its own length, and it must agree with what AW promised.

2. WLAST Timing

On the waveform, WLAST is high for exactly the final beat's transfer and low for all earlier beats.

WLAST — asserted on the final beat only

7 cycles

Figure 1 — WLAST timing for a 4-beat write (AWLEN=3). WLAST is low for beats 0–2 and asserted only on beat 3 (the AWLEN+1-th), where it transfers with the last WDATA. That beat ends the data phase and is the gate the subordinate waits for before it may drive B. WLAST on the wrong beat means the burst length disagrees with AWLEN.

A subtle but common bug: a burst whose WLAST never asserts (off-by-one length logic, or a counter that misses) leaves the subordinate waiting forever for the data phase to end — so it never drives B and the write hangs. WLAST isn't optional bookkeeping; it's the terminator the whole transaction depends on.

3. AW ↔ W Ordering — Independent, but Paired by Order

AW and W are independent channels (Chapter 2.4): in AXI4 the write data may arrive before, with, or after the write address. A manager that already has data ready can stream W beats before the AW handshake; another can send AW first and W later. The subordinate must accept either timing.

Figure 2 — AW and W are independent in time. The write data on W may be presented before, simultaneously with, or after the address on AW; the subordinate accepts any of these orderings. What it must NOT rely on is a fixed AW-then-W timing — the channels are decoupled, and pairing is by transaction order, not arrival timing.

But independent timing does not mean arbitrary pairing. Because AXI4 has no WID, the subordinate pairs them by order: the first AW pairs with the first complete W burst (the one ending in its WLAST), the second with the second, and so on. So the rule is: addresses are issued in order, write-data bursts are delivered in order, and the Nth burst belongs to the Nth address — regardless of the relative timing of the two channels.

4. The Write-Data Ordering Rule

Stated precisely for AXI4: a manager must deliver its write-data bursts in the same order it issued the addresses, one complete burst at a time. No interleaving — a transaction's beats (through WLAST) all come before the next transaction's first beat. This is what lets the subordinate pair W to AW by order without any ID.

Figure 3 — pairing by order. Addresses AW0 then AW1 are issued in order; the W channel delivers burst 0 in full (through its WLAST), then burst 1 in full. The subordinate pairs burst 0 → AW0 and burst 1 → AW1 by position. Because bursts are not interleaved, no WID is needed to tell them apart.

In subordinate terms, this is a clean queue — no per-ID reassembly:

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Snippet

// Conceptual — AXI4 pairs the Nth write-data burst to the Nth address, in order.
// (No WID: write data is NOT interleaved, so just collect one full burst at a time.)
always @(posedge aclk) begin
  if (awvalid && awready)            aw_q.push('{awid, awaddr, awlen}); // addresses in order
  if (wvalid && wready) begin
    cur_burst.push(wdata, wstrb);
    if (wlast) begin
      txn = aw_q.pop();              // this completed burst belongs to the oldest AW
      apply_write(txn, cur_burst);   // pair by order — no ID matching needed
      cur_burst.clear();
    end
  end
end

5. AXI3 → AXI4: The WID Change

This is where the history matters. AXI3 had a WID signal on the write-data channel, and it existed for one purpose: to allow write-data interleaving — beats from different outstanding write transactions could be mixed together on the W channel, each beat tagged with the WID of the transaction it belonged to, so the subordinate could sort them out.

AXI4 removed WID and forbade write-data interleaving. Write data must now be sent in address order, one full burst at a time — exactly the rule above. The trade was deliberate: interleaving added significant complexity to subordinates (per-ID write-data reassembly buffers) for little real-world benefit, since most masters didn't interleave anyway. Removing it makes AXI4 write subordinates much simpler.

Figure 4 — AXI3 vs AXI4 write data. AXI3 allowed interleaving: beats from transaction A and B mixed on W, each tagged by WID, requiring the subordinate to reassemble per ID. AXI4 removed WID and forbids interleaving: each transaction's burst is contiguous and in address order, so the subordinate needs no reassembly. A bridge from AXI3 to AXI4 must de-interleave.

The practical fallout: bridging AXI3 → AXI4 requires de-interleaving the WID-tagged write data into contiguous, in-order bursts (and dropping WID); bridging the other way may need to add it. It's one of the specific behaviours a generation converter must reconcile (Chapter 2.5).

6. Common Misconceptions

Myths to unlearn

"WLAST is just informational." It's the data-phase terminator: it tells the subordinate the write data is complete and gates B. A burst that never asserts WLAST hangs the write.
"Write data must come after the address." In AXI4, W may precede, accompany, or follow AW — the channels are independent. Only the order across transactions is fixed, not the AW-vs-W timing within one.
"The subordinate uses an ID to match W data to AW." In AXI4 there's no WID; it pairs by order — the Nth full W burst belongs to the Nth address. IDs (AWID/BID) tag the transaction and its response, but not the W beats.
"AXI4 still supports write-data interleaving." No — AXI4 removed WID and forbids interleaving. Interleaving was an AXI3 feature.
"WLAST can be anywhere as long as the data's right." WLAST must land on beat AWLEN+1. Early/late WLAST means the burst length disagrees with AW — a protocol violation.

7. Debugging Insight

🔍 Debugging insight — WLAST position and burst order are the usual culprits

Most write-ordering bugs reduce to two checks:

Does WLAST land on beat AWLEN+1? Capture the AW handshake (for AWLEN), then count W beats to the WLAST. WLAST too early → the subordinate thinks the write ended short (wrong length, premature B); WLAST too late or missing → the data phase never ends, B never comes, the write hangs. This single alignment check catches a large fraction of write bugs.
Are W bursts contiguous and in address order? On AXI4, two transactions' beats interleaved on W is illegal — look for a WLAST arriving with fewer beats than the oldest AW expected, or beats that belong to a later transaction appearing before the current burst's WLAST. This is almost always an AXI3-style master or an un-de-interleaved bridge.
Cross-check pairing. If write data lands at the wrong address, verify the order: did the manager issue addresses and bursts in matching order? A reordered burst pairs to the wrong AW and writes the right data to the wrong place — with no ID to catch it, order is the only pairing.

Anchor on AWLEN for WLAST position and on issue order for pairing; those two cover the ordering/WLAST failure space.

8. Verification Insight

✅ Verification insight — assert WLAST alignment and no-interleaving

The ordering rules become targeted assertions and pointed stimulus. Assertions: WLAST must assert exactly on the AWLEN+1-th W beat of each burst (not earlier, not later), every write burst must eventually produce a WLAST (liveness — a missing one is a hang), and on AXI4 write data must not interleave across transactions (each burst contiguous through its WLAST). Stimulus: drive all three legal AW/W timings — W-before-AW, W-with-AW, W-after-AW — and multiple outstanding writes, because a subordinate that secretly assumes AW-then-W only breaks when you present data first; vary burst lengths so off-by-one WLAST logic is exposed; include single-beat writes (AWLEN=0, WLAST on beat 0). The monitor pairs each completed W burst to its AW by order and feeds the scoreboard, so a mis-paired (reordered) burst surfaces as a data-at-wrong-address mismatch.

For AXI3 interop, add coverage of interleaved WID traffic on the AXI3 side of a bridge and assert it emerges de-interleaved and in-order on the AXI4 side. Mechanics in Module 16.

9. Interview Questions

10. Summary

A write is decoupled across three channels but remains one transaction, tied together by WLAST and ordering. WLAST terminates the data phase: it must assert on beat AWLEN+1, it tells the subordinate the data is complete, and it gates B (B-after-W). A missing or mis-placed WLAST either hangs the write or makes the burst length disagree with AW. AW and W are independent in time — in AXI4 the data may precede, accompany, or follow the address — but they are paired by order: the Nth complete W burst belongs to the Nth address, because AXI4 has no WID and forbids write-data interleaving.

That last point is the AXI3→AXI4 change: AXI3's WID allowed interleaved write data (requiring per-ID reassembly in the subordinate); AXI4 removed it for simplicity, mandating contiguous, in-order bursts — so an AXI3→AXI4 bridge must de-interleave. Debug by checking WLAST position against AWLEN and confirming W bursts are contiguous and in issue order; verify with WLAST-alignment and no-interleaving assertions plus all-three AW/W timings. With ordering and WLAST settled, the last write topic is decoding the response itself.

11. What Comes Next

The write path is nearly complete; only the response semantics remain:

4.5 — BRESP & Write Response Timing (coming next) — decoding BRESP (OKAY/EXOKAY/SLVERR/DECERR) and exactly when B may arrive.
4.6 — Write Transaction Waveforms (coming soon) — annotated end-to-end write waveforms (single, burst, stalled).

Previous: 4.3 — The Write Response (B) Channel. For the broader protocol catalog, see the AMBA family overview doc.