AMBA AXI · Module 4

The Write Data (W) Channel

The AXI W channel in detail — WDATA, the WSTRB byte strobes that enable partial writes, beat sequencing, WLAST, and why AXI4 dropped WID.

AW declared the shape of the write; the W (write data) channel delivers the bytes. It carries three things per beat — WDATA (the data), WSTRB (byte-lane strobes that say which bytes are valid), and WLAST (the end-of-burst marker) — and it delivers exactly the AWLEN+1 beats AW promised. The signal that makes W more than "just data" is WSTRB: it lets a write touch only some bytes of a beat, which is how AXI does partial and unaligned writes — and getting it wrong corrupts memory silently. This chapter details WDATA/WSTRB/WLAST, the beat sequencing, and why AXI4 removed WID. Burst-address math and strobe-in-burst corner cases are Module 6–7; here it's the W channel itself.

1. W Delivers the Data the AW Shape Described

If AW is "where and what shape," W is "here are the bytes." Each W beat carries one transfer's worth of data, and the manager streams AWLEN+1 of them to fulfill the burst AW launched. W is decoupled from AW (Chapter 2.4): in AXI4 the data may arrive before, with, or after the address — the subordinate pairs W data to its AW by transaction order, not by timing.

Three signals per beat (plus the WVALID/WREADY handshake):

WDATA — the data for this beat, as wide as the data bus.
WSTRB — one byte-lane strobe per byte of WDATA: bit i says "byte i of WDATA is valid — write it."
WLAST — asserted on the final beat of the burst.

Figure 1 — the W channel's signals. WDATA carries the bytes; WSTRB marks which of those bytes are actually written (one strobe bit per byte lane); WLAST flags the last beat. WVALID/WREADY transfer one beat at a time. Unlike a read's R channel, W has no per-beat response and (in AXI4) no ID.

2. WSTRB — The Byte-Lane Strobes

WSTRB is the W channel's defining feature and the read path's nothing-equivalent. There is one strobe bit per byte lane of the data bus (a 32-bit bus has 4 strobe bits; a 128-bit bus has 16). Strobe bit i gates byte i of WDATA: if set, the subordinate writes that byte; if clear, it leaves the corresponding memory byte untouched.

This is the mechanism for partial and sparse writes. Writing a single byte into a 16-byte-wide bus means asserting one strobe bit and clearing the other fifteen. An unaligned or sub-word write (a CPU storing a byte or halfword) becomes a full-width beat with only the relevant strobes set. The subordinate must honor the strobes exactly:

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Snippet

// Conceptual — a W beat, and how WSTRB masks the write per byte lane.
typedef struct packed {
  logic [DW-1:0]   wdata;   // data for this beat
  logic [DW/8-1:0] wstrb;   // byte-lane enables: bit i ↔ wdata[8*i +: 8]
  logic            wlast;   // 1 on the final beat of the burst
} w_beat_t;
 
// At the subordinate: write ONLY the enabled byte lanes.
for (int i = 0; i < DW/8; i++)
  if (wstrb[i])
    mem[addr][8*i +: 8] = wdata[8*i +: 8];   // bytes with wstrb[i]=0 are untouched

The classic bug is a subordinate that ignores WSTRB and writes the whole beat: now a sub-word write clobbers the bytes that should have been preserved — silent corruption that only shows when someone reads those neighboring bytes back. WSTRB is mandatory to honor, not optional.

Figure 2 — WSTRB selecting byte lanes. On a 4-byte beat with WSTRB = 0b0110, only byte lanes 1 and 2 are written; lanes 0 and 3 are skipped and their memory bytes keep their old values. This is how AXI writes a halfword (or any sub-word/unaligned span) within a full-width beat — and a subordinate that ignores WSTRB would corrupt lanes 0 and 3.

3. WLAST and Beat Sequencing

WLAST marks the final beat of the write burst. The manager streams beats — WDATA/WSTRB for beat 0, beat 1, … — and asserts WLAST on beat number AWLEN+1 (the last). The subordinate uses WLAST to know the data phase is complete (and, per Module 3, only then may it assert BVALID). A single-beat write (AWLEN=0) asserts WLAST on its one and only beat.

The beat count is the contract from AW: the manager must deliver exactly AWLEN+1 W beats and assert WLAST on the last one. Delivering too few, too many, or asserting WLAST on the wrong beat is a protocol violation that leaves the write malformed (and often hangs the transaction, since the subordinate is waiting for the WLAST that defines completion). The W channel doesn't re-send the address or length — it just produces the agreed number of beats in order.

Figure 3 — beat sequencing. AW declared an 8-beat burst (AWLEN=7); the W channel delivers beats 0..7 in order, each with its WDATA and WSTRB, and asserts WLAST on beat 7. The count and order are fixed by AW; W simply fulfills them, and WLAST closes the data phase.

4. No WID in AXI4

A signal you might expect but won't find: AXI4 has no WID. In AXI3, write data carried a WID so that write data from different transactions could be interleaved on the W channel. AXI4 removed both: write data must be delivered in the same order as the addresses were issued, one transaction's full burst before the next's, so there's no need to tag each W beat with an ID. (AXI4-Stream and the read channel have their own IDs; the memory-mapped write data channel simply doesn't in AXI4.)

The practical consequence: with AXI4, the W beats for outstanding writes are not interleaved — they go in AW-issue order. This simplifies subordinates (no per-ID write-data reassembly) and is one of the AXI3→AXI4 cleanups from Chapter 2.5. If you're bridging from AXI3, de-interleaving WID-tagged write data into AXI4's in-order stream is part of the converter's job.

5. The W Beats on a Waveform

A burst on the W channel: WVALID/WREADY move one beat per cycle, WDATA (and WSTRB) change each beat, and WLAST rises on the final one.

W channel — a 4-beat write burst

7 cycles

Figure 4 — four W beats fulfilling an AWLEN=3 burst. WVALID and WREADY are high across cycles 1–4, so D0..D3 transfer one per cycle, each with full byte strobes (WSTRB=0xF here); WLAST asserts on cycle 4 (the 4th beat), closing the data phase. The beat count (4) matches AWLEN+1.

6. Common Misconceptions

Myths to unlearn

"Every byte of WDATA is written." Only the byte lanes whose WSTRB bit is set are written; the rest are left untouched. A subordinate that ignores WSTRB silently corrupts the bytes that should have been preserved.
"WSTRB is only for unaligned writes." Any partial/sparse write uses it — sub-word stores, byte/halfword accesses, masked writes. It's a general byte-enable, not just an alignment fixup.
"W carries the address or length." It doesn't — W carries only data, strobes, and WLAST. The address and beat count were declared on AW; W just delivers the agreed beats in order.
"AXI4 write data has a WID." No — AXI4 removed WID and forbids write-data interleaving; data goes in AW-issue order. WID existed only in AXI3.
"WLAST is optional / the slave counts beats itself." WLAST is the explicit end-of-data marker the subordinate relies on to complete the write (and gate B). A burst that never asserts WLAST hangs the transaction.

7. Debugging Insight

🔍 Debugging insight — check W against AW, and always inspect WSTRB

The W channel's bugs are mostly disagreements with AW plus the strobe trap:

Count the W beats against AWLEN. Capture the AW handshake, then count WVALID && WREADY beats. Fewer or more than AWLEN+1, or WLAST on the wrong beat, is a length-mismatch — the master and the AW it issued disagree, and the subordinate (waiting for WLAST) may hang.
When data is wrong but the beat looks fine, read WSTRB. Corrupted neighboring bytes after a sub-word write means the subordinate ignored the strobes (wrote the whole beat). Wrong bytes written means the strobes themselves were mis-driven (wrong lanes set). WSTRB is the first thing to check on any "write wrote the wrong bytes" bug.
Confirm strobe/address alignment. The set strobe lanes should correspond to the addressed bytes; a mismatch between AWADDR's low bits and which WSTRB lanes are active indicates a byte-lane-steering bug (common in width converters).
Watch for interleaving on AXI4. Two transactions' W beats mixed together is an AXI3-style violation on an AXI4 bus — often a bridge that didn't de-interleave.

Anchor on AW for count/shape, and treat WSTRB as a first-class signal — it's invisible to a casual "data looks right" glance but is exactly where partial-write corruption hides.

8. Verification Insight

✅ Verification insight — WSTRB is the write-scoreboard's make-or-break detail

A write scoreboard's correctness hinges on modeling WSTRB: it must update its reference memory only on the byte lanes the strobe enabled, exactly like the DUT. The most common write-verification bug is a scoreboard that applies the whole WDATA and then mismatches the DUT on every partial write — or, worse, masks a real strobe bug by also ignoring strobes. So the reference model does if (wstrb[i]) ref[addr][i] = wdata[i]; per lane, beat by beat.

The stimulus must exercise partial writes: random WSTRB patterns including single-lane, sparse, all-zero (a legal no-op beat), and full strobes, across varied AWSIZE/AWBURST/alignment — not just full-width beats. Assertions bind to W as well: the W-beat count equals AWLEN+1 with WLAST on the last, the handshake obeys stability/cardinal rules (Module 3), and (AXI4) write data is not interleaved across transactions. Coverage wants the cross of strobe patterns × beat positions (first/middle/last) × burst types. Because WSTRB is where partial-write correctness lives, it's where the write scoreboard earns its keep. Mechanics in Module 16.

9. Interview Questions

10. Summary

The W channel delivers the bytes AW's shape described: each beat carries WDATA, WSTRB, and WLAST, moved by the WVALID/WREADY handshake. WSTRB is the channel's defining signal — one strobe per byte lane, enabling partial and sparse writes by writing only the marked bytes and leaving the rest untouched; a subordinate must honor it exactly or it silently corrupts neighboring bytes. WLAST marks the final beat, and the manager must deliver exactly AWLEN+1 beats in order with WLAST on the last — the count is the contract from AW, not re-sent on W. And AXI4 has no WID: write-data interleaving is forbidden, so data flows in AW-issue order (the AXI3 cleanup).

Debug W by anchoring on AW (count beats, check WLAST position) and treating WSTRB as first-class (it's where partial-write corruption hides); verify it with a scoreboard that masks by WSTRB per lane and stimulus that exercises sparse strobes and alignments. With the address (AW) and data (W) channels covered, only the write's acknowledgement remains — the B channel.

11. What Comes Next

The data has been delivered; the write isn't done until it's confirmed:

4.3 — The Write Response (B) Channel (coming next) — why a write needs an explicit response, and BRESP/BID semantics.
4.4 — Write Ordering & WLAST (coming soon) — ordering, WLAST, and the AXI3→AXI4 WID change in depth.

Previous: 4.1 — The Write Address (AW) Channel. For the broader protocol catalog, see the AMBA family overview doc.

Standards & specifications

Governing standard: Arm AMBA AXI Protocol Specification (IHI 0022)(opens Arm in a new tab)
Defines the AXI channels, handshake and ordering rules. RTL structure, interconnect topology and verification strategy are design choices this specification does not mandate.

This page also covers RTL structure, verification approach and debugging technique. Those are engineering practice built on the standard, not requirements the standard itself imposes.

Where this fits

Part of the AMBA AXI curriculum.