AXI4 vs AXI3 vs AXI4-Lite vs AXI4-Stream

"AXI" is not one protocol — it's a family, and the first thing an engineer must do when handed an AXI interface is answer which AXI is this? Get it wrong and your mental model, your RTL, and your testbench are all aimed at the wrong target. There are four members worth knowing: AXI4 (the full memory-mapped workhorse), AXI3 (its predecessor), AXI4-Lite (a stripped-down register subset), and AXI4-Stream (a different animal entirely — addressless streaming). This chapter maps what each keeps or drops and when to reach for it, closing Module 2 so that by Module 3 you always know exactly which variant's rules apply.

1. One Name, Four Protocols

The four variants split into two groups by a single question: is there an address?

• Memory-mapped variants — AXI4, AXI3, AXI4-Lite — all transact at an address: a manager reads/writes a location, using the AW/W/B and AR/R channels you've already met. They differ in how much of the full protocol they carry.
• Stream — AXI4-Stream — has no address at all. It is a point-to-point data pipe: a producer pushes data to a consumer, beat after beat. It shares AXI's VALID/READY handshake philosophy but none of its addressing.

So three of the four are "the AXI you know, dialled up or down," and the fourth is a separate streaming protocol that borrowed the handshake. Holding that split prevents the most common confusion — expecting addresses or bursts on a stream, or expecting stream framing on a memory-mapped bus.

2. AXI4 — The Full Memory-Mapped Workhorse

AXI4 is the default modern variant and the one this whole track teaches: five channels (AW/W/B/AR/R), the VALID/READY handshake, bursts up to 256 beats, transaction IDs for outstanding and out-of-order traffic, and the full set of attributes (AxSIZE, AxBURST, AxCACHE, AxPROT, plus AXI4 additions like AxQOS and AxREGION). It is what high-bandwidth masters and memory controllers speak. When someone says "AXI" with no qualifier in a modern design, they almost always mean AXI4 — so it's the right baseline, and the other three are best understood as deltas from it.

3. AXI3 — The Predecessor

AXI3 is the earlier generation. It is memory-mapped like AXI4 and looks almost identical, but a handful of differences matter — and they're favourite interview material precisely because they're the "what changed" details:

• Burst length: AXI3 bursts are limited to 16 beats (AxLEN is 4 bits); AXI4 extended this to 256 beats (AxLEN 8 bits) for INCR bursts.
• Write data interleaving: AXI3 allowed interleaving write data from different transactions; AXI4 removed it (it complicated slaves for little gain).
• WID: AXI3 had a write-data ID (WID) to support that interleaving; AXI4 dropped WID since write data must now arrive in order per transaction.
• Locked transactions: AXI3 supported locked (atomic-by-locking) accesses; AXI4 removed locked support, keeping only exclusive access.
• AXI4 added AxQOS (quality-of-service) and AxREGION (region identifier).

You meet AXI3 mainly when integrating older IP. The takeaway isn't to memorize the table now — it's to know that "AXI3" signals shorter bursts, possible write interleaving, WID, and locked access, none of which a clean AXI4 design has.

4. AXI4-Lite — The Register Subset

AXI4-Lite is AXI4 with the performance machinery removed, for traffic that doesn't need it — control and status registers. It keeps the five-channel structure and the handshake but drops nearly everything else:

• Single beat only — no bursts (AxLEN effectively fixed at one transfer; every access moves exactly one data beat).
• No transaction IDs — so no out-of-order, minimal outstanding; transactions are simple and ordered.
• Fixed data width (32 or 64 bits) and a trimmed attribute set.

The result is an interface trivial to implement and verify — perfect for a peripheral's register block, and the near-universal control-plane interface for IP. It is the AXI analogue of "use APB for registers," but staying within the AXI family so a single fabric can carry it. The cost is exactly the capability it removed: no bursts, no concurrency — which registers don't want anyway.

5. AXI4-Stream — The Addressless Sibling

AXI4-Stream is the odd one out, and the most misunderstood. It is not memory-mapped — there is no address, no read/write direction, no AW/AR. It is a one-way data pipe from a producer to a consumer, carrying a stream of beats with its own T-prefixed signals:

• TDATA — the payload; TVALID/TREADY — the same handshake idea; TLAST — marks the end of a packet/frame.
• TKEEP/TSTRB — which bytes are valid; TID/TDEST — routing/identification for stream interconnect; TUSER — sideband.

Because there's no address, you don't "read from" or "write to" a stream — data just flows when both sides are ready, framed into packets by TLAST. It's the natural fit for DMA, video pixels, and network packets — anything that is a continuous flow rather than addressed accesses. Conceptually it's addressless flow:

// Conceptual — one AXI4-Stream beat. Note what is ABSENT: no address, no ID
// to route by location, no read/write. Just payload, byte-enables, end-of-packet.
typedef struct packed {
  logic [DW-1:0]   tdata;   // the payload for this beat
  logic [DW/8-1:0] tkeep;   // which bytes are valid
  logic            tlast;   // 1 = last beat of the packet/frame
} axis_beat_t;

The full stream signal set and packet semantics are Module 11; here, the one thing to lock in is AXI4-Stream has no address — it is flow, not addressed access.

6. Side by Side

The four variants across the features that distinguish them:

Read it as: AXI4 is the full set; AXI3 is AXI4 minus the AXI4 cleanups (so it has WID, interleaving, locked, but shorter bursts); AXI4-Lite is AXI4 minus bursts/IDs/concurrency; AXI4-Stream is a different protocol that kept only the handshake.

7. Choosing a Variant

In practice the choice is a short decision, driven by what the traffic is:

A single SoC commonly uses all four: AXI4 for the CPU/DMA-to-memory fabric, AXI4-Lite for peripheral registers, AXI4-Stream for a video or DMA data pipe, and AXI3 wherever a piece of older licensed IP only speaks the earlier generation.

8. The AXI3 → AXI4 Cleanup, in One Picture

Because the AXI3↔AXI4 deltas are such common interview fodder, it's worth isolating what the newer generation changed:

9. Common Misconceptions

10. Debugging Insight

11. Verification Insight

12. Interview Questions

13. Summary

"AXI" names a family of four. AXI4 is the full memory-mapped workhorse — five channels, bursts to 256 beats, IDs, outstanding and out-of-order — and the right baseline. AXI3 is the earlier memory-mapped generation: shorter (16-beat) bursts, write-data interleaving with WID, and locked access, all of which AXI4 cleaned up (and AXI4 added AxQOS/AxREGION). AXI4-Lite is AXI4 with the performance machinery removed — single-beat, no IDs, no bursts — the trivial-to-build interface for control registers. AXI4-Stream is the outlier: addressless point-to-point flow with T-signals and TLAST framing, for DMA, video, and packets.

The discipline is to identify the variant first — it decides whether addresses, bursts, IDs, or out-of-order behaviour even exist, and therefore what you design, debug, and verify. A real SoC runs several variants at once, each matched to its traffic. With the architecture and variants mapped, Module 3 zooms into the one contract every memory-mapped channel shares and every variant inherits: the VALID/READY handshake.

14. What Comes Next

That closes Module 2 — AXI Architecture: five channels, the read and write paths, why decoupling matters, and the four variants. Module 3 goes deep on the single contract underneath all of it:

• 3.1 — The VALID/READY Handshake (coming next) — the transfer contract every AXI channel uses, the rule that prevents deadlock, and the waveform every engineer must read on sight.

Previous: 2.4 — Independent Channels & Decoupling. For the broader protocol catalog, see the AMBA family overview doc.