Skip to content
VLSI Mentor

ProgramsCareer path

DFT Engineer

DFT engineers make digital designs testable after fabrication and build the structures and flows required to detect manufacturing defects.

Starting point
Verilog RTL and basic digital design
Path
Foundation → Specialization
Learning modes
Tutorials
VLSI Mentor coverage
7 available of 8 stages

01What to learn, in order

The industry roadmap for this role. Stages without content yet are listed anyway — knowing the gap is more useful than a shorter map.

  1. Manufacturing test & fault models

    Available

    A defect is not a design bug. Stuck-at, transition and bridging models are how physical failures become something a tool can target.

    Design for Testability

  2. Testability: controllability & observability

    Available

    A fault can only be detected if it can be activated and its effect propagated to an observable point — that is the whole DFT problem in one sentence.

    Design for Testability

  3. Scan architecture & insertion

    Available

    Scan turns every flop into a controllable and observable point, converting an unreachable sequential problem into a combinational one.

    Design for Testability

  4. ATPG

    Available

    Once scan structures exist, patterns must be generated that activate modeled faults and propagate their effects to observable points.

    Design for Testability

  5. Scan compression

    Available

    Pattern volume is tester time, and tester time is cost — compression keeps coverage while shrinking what has to be shifted in.

    Design for Testability

  6. MBIST & boundary scan

    Available

    Memory arrays and board-level interconnect cannot be covered by logic ATPG, so they need their own built-in and JTAG-based test structures.

    Design for Testability

  7. DFT verification & gate-level debug

    Available

    Test structures are RTL too: they must be verified, and their failures surface at gate level with real timing rather than in RTL simulation.

    Design for TestabilityGate Level Simulation

  8. DFT labs

    Curriculum in development

    Scan chains, coverage loss and chain failures are best understood by inserting, running and debugging them on a real design.

02What you should be able to do

Reason
Explain why manufacturing test exists and what it actually checks.
Read
Interpret fault models and a test-coverage report.
Design
Reason about scan architecture, chain count and balancing.
Implement
Follow scan insertion, ATPG and compression through the flow.
Debug
Trace coverage loss and scan-chain failures at gate level.
All engineering paths