Why Reset Design Matters

1. Engineering intuition — start from a known state

Combinational logic has no state to initialise, but every flip-flop holds a value — and at power-up that value is undefined. A state machine could wake in an illegal state; a counter could start at any number; a valid flag could come up asserted when nothing is valid. Worse, those unknowns propagate: anything computed from an uninitialised register is itself unknown (lesson 3.8). Reset solves this by forcing chosen flip-flops to a defined value, so the design begins in a known, legal condition and behaves the same every time it powers up. Reset is how you guarantee a correct starting point.

2. Formal explanation — reset gives state a defined value

library ieee; use ieee.std_logic_1164.all;
-- A reset forces state to a known value; here a synchronous reset (Module 8 details the kinds).
process (clk)
begin
  if rising_edge(clk) then
    if rst = '1' then state <= IDLE;          -- defined start (legal state)
    else              state <= next_state;
    end if;
  end if;
end process;

Reset is an input that, when asserted, drives selected state elements to their defined initial value (an FSM to its idle state, a counter to zero, a valid flag low). Without it, those elements hold their power-up unknown until something happens to overwrite them. The reset value is a design choice — usually the "idle/inactive/zero" state — so an un-exercised path still begins safe. (Recall from lesson 3.8 that a signal initializer := '0' is honoured by simulation and FPGA bitstreams but not by ASIC flip-flops, which is exactly why a real reset is needed.)

3. Production RTL — what needs reset, what often does not

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
ctrl : process (clk)
begin
  if rising_edge(clk) then
    if rst = '1' then
      state    <= IDLE;                 -- MUST reset: control state must start legal
      valid    <= '0';                  -- MUST reset: a status flag must start known
      count    <= (others => '0');      -- usually reset: counters start defined
    else
      state <= next_state;
      valid <= in_valid;
      if en = '1' then count <= count + 1; end if;
      data_q <= data_in;                -- NO reset: datapath reg overwritten before use
    end if;
  end if;
end process;

What hardware does this become? The control/state flip-flops (state, valid, count) get a reset connection so they start known; the datapath register data_q has no reset because its value does not matter until it is loaded and consumed — leaving it un-reset saves a reset net (area and routing) on what is often the bulk of the registers. This selective reset is a real optimisation in large designs.

4. Hardware interpretation — unknown vs known start, and reset distribution

5. Simulation interpretation — X until reset, then known

6. Debugging example — the design that works in sim but not silicon (or vice versa)

Expected: the design starts correctly on hardware. Observed: it works in RTL simulation but misbehaves at power-up on an ASIC (or works on FPGA but not ASIC). Root cause: state relied on a signal initializer (:= …) or on simulation's defined startup, but the ASIC flip-flops power up unknown with no reset to a known value — so real silicon starts in garbage that simulation did not show. Fix: give all control/state elements an explicit reset to a defined value (do not rely on initializers for ASIC startup). Engineering takeaway: simulation and FPGA can mask a missing reset because they define power-up state; ASIC flip-flops do not — control and state must be reset explicitly to start known.

-- RISKY: relies on an initializer; ASIC flip-flops ignore it → unknown start.
-- signal state : state_t := IDLE;        -- sim/FPGA only
-- ROBUST: explicit reset to a known state.
if rising_edge(clk) then
  if rst = '1' then state <= IDLE; else state <= next_state; end if;
end if;

7. Common mistakes & what to watch for

• No reset on control/state. FSM state, valid flags, and counters must start known; missing reset means unknown power-up and X propagation.
• Relying on := initializers for ASIC. They work in sim and FPGA bitstreams but not ASIC flip-flops; use a real reset for portable startup.
• Resetting everything indiscriminately. Datapath registers overwritten before use often need no reset; resetting them wastes nets, area, and routing in large designs.
• Choosing a bad reset value. Reset to the safe/idle/inactive value so an un-exercised path begins benign.
• Ignoring the reset-release timing. How reset de-asserts relative to the clock matters (metastability) — covered later in the module.

8. Engineering insight & continuity

Reset is the guarantee that your design starts from a known, correct state rather than the silicon's random power-up — and good reset design is as much about which registers to reset as how. Reset the control and state that must begin legal (FSM state, flags, counters); skip datapath registers that are overwritten before use, to save reset nets in large designs. With the role of reset established, the module makes the key decision concrete: the next lessons cover Synchronous Reset and Asynchronous Reset, their trade-offs, the subtle reset-release / metastability issue, and the best practices that tie them into a robust reset strategy.