VHDL · Topic
VHDL Sequential Logic — Registers, Counters & State Machines
Clocked processes, synchronous and asynchronous reset, counters, shift registers and finite state machines in VHDL.
Sequential logic in VHDL is a clocked process and a small set of conventions that synthesis recognises. The conventions matter more than they look: where the reset is tested decides whether it is synchronous or asynchronous, and which signals are assigned on every path decides whether you get a register or an unintended latch. A state machine written without a default assignment inherits state it was never meant to hold.