Modeling Sequential Logic

1. Engineering intuition — logic with memory, on a clock

Sequential logic remembers. Where a combinational block answers "what is the output for these inputs right now," a sequential block answers "what is the output given these inputs and everything that happened before." That history lives in state — values stored in registers — and the state only changes at a clock edge, one tick at a time. Counters, shift registers, state machines, and every pipeline are sequential: they hold state and advance it on the clock. The discipline that makes this reliable is synchronous design — one clock, all registers updating on its edge.

2. Formal explanation — the clocked process and synchronous rules

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
-- The canonical sequential description: a clocked process with reset.
reg : process (clk)
begin
  if rising_edge(clk) then            -- update state ONLY on the rising edge
    if rst = '1' then state <= IDLE;  -- synchronous reset to a defined start
    else              state <= next_state;
    end if;
  end if;
end process;

A sequential element is described by a clocked process: sensitive to the clock, with the state assignment guarded by rising_edge(clk) so it updates only on the edge (a flip-flop). The synchronous rules: (1) all state updates on the same clock edge; (2) state lives in registers (one <= per state signal under the edge guard — no default; the register holds when not assigned); (3) a reset defines the power-on/initial state. Follow these and the design is a clean network of flip-flops and combinational logic between them.

3. Production RTL — state, next-state, and output

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
-- Clocked process: holds the state register (sequential).
state_reg : process (clk)
begin
  if rising_edge(clk) then
    if rst = '1' then count <= (others => '0');
    else              count <= count_next;        -- register: holds between edges
    end if;
  end if;
end process;
 
-- Combinational process: next-state / output logic (Module 6 patterns).
next_logic : process (all)
begin
  count_next <= count;                            -- default: hold
  if en = '1' then count_next <= count + 1; end if; -- next-state function
  tc <= '1' when count = MAX else '0';            -- output (here combinational)
end process;

What hardware does this become? A counter: a register (count) updated on the clock edge, fed by combinational next-state logic (count + 1 when enabled), with a terminal-count output. This registered-state + combinational-next-state split is the template for all sequential logic — keep the clocked process for state and a combinational process (Module 6) for the next-state/output function.

4. Hardware interpretation — registers and the logic between them

5. Simulation interpretation — state advances one edge at a time

6. Synthesizer interpretation — flip-flops plus logic

Synthesis maps a clocked process to flip-flops: each state signal assigned under rising_edge(clk) becomes a register, and the expressions feeding it become the combinational next-state logic between registers. The clock connects to every flip-flop's clock pin; the reset connects to their reset. This is why the synchronous rules matter — one clock edge means one clock domain of flip-flops that update together, which static timing analysis can constrain (setup/hold against that clock). Mixed edges or gated clocks (later lessons) complicate exactly this.

7. Debugging example — combinational where sequential was meant (and vice versa)

Expected: a register that holds state. Observed: no register inferred (the value does not hold), or an inferred latch. Root cause: the clock-edge guard (rising_edge(clk)) was missing, so the process is combinational (no flip-flop), or the logic was written combinationally with an unassigned path (a latch) instead of in a clocked process. Fix: put state in a clocked process guarded by rising_edge(clk) (and reset); keep next-state/output logic in a separate combinational process with defaults. Engineering takeaway: registers come only from a clock-edge-guarded assignment; if you want stored state, it must live under rising_edge(clk).

-- BUG: no clock guard → combinational (does not hold) or, with partial assignment, a latch.
-- process(all) begin if en='1' then q <= d; end if; end process;
-- FIX: clocked process → a real register that holds.
process (clk) begin
  if rising_edge(clk) then
    if en = '1' then q <= d; end if;     -- register with enable; holds when en='0'
  end if;
end process;

8. Common mistakes & what to watch for

• Missing the clock-edge guard. State must be assigned under rising_edge(clk); without it you get combinational logic or a latch, not a register.
• Defaulting a registered output. A register should hold when not assigned; do not give it a combinational-style default every cycle.
• Multiple clock edges / domains carelessly mixed. Keep one clock per process; crossing domains needs synchronisers (later module).
• Putting next-state logic inside the clocked process unnecessarily. It works, but separating combinational next-state from the clocked register is clearer and matches the model.
• Forgetting reset. Define state on reset so the design starts known (Module 8 covers reset in depth).

9. Engineering insight & continuity

Sequential logic is combinational logic plus memory on a clock — and the entire module rests on the clocked process: state in registers, updated on one clock edge, defined by reset. The register that broke the combinational loop in the last lesson was the seed; this module grows it into the full toolkit of synchronous design. With the model established, the next lessons make each piece precise: Detecting the Clock Edge (rising_edge/falling_edge and why), the D Flip-Flop and Registers, Clock Enable, Counters, Shift Registers, and the subtleties of gated clocks and signal-versus- variable registers — every building block of stateful hardware.