All Verilog HDL labs
Verilog HDL Labs
Lab 12of 60
Logic Foundations8
Combinational Design14
- 9Carry-Lookahead Adder
- 10Configurable Adder-Subtractor
- 11BCD Adder
- 12Multiplexer Family
- 13Demultiplexer
- 14Binary Decoder
- 15Binary Encoder
- 16Priority Encoder
- 17Magnitude Comparator
- 18Parity Generator and Checker
- 19Binary-to-Gray and Gray-to-Binary Converter
- 20BCD-to-Seven-Segment Decoder
- 21Barrel Shifter
- 22Four-Bit Arithmetic Logic Unit
Sequential Design14
- 23SR Latch
- 24Gated D Latch
- 25D Flip-Flop with Synchronous and Asynchronous Reset
- 26JK Flip-Flop
- 27T Flip-Flop
- 28Flip-Flop Conversions
- 29Edge and One-Cycle Pulse Detector
- 30SISO Shift Register
- 31SIPO Shift Register
- 32PISO Shift Register
- 33PIPO Register
- 34Bidirectional Shift Register
- 35Universal Shift Register
- 36Eight-Word Register File
Counters & Timing10
Finite State Machines8
Memory & Reusable Blocks4
Portfolio Projects2
Combinational DesignPublished
Multiplexer Family
2:1 through 16:1 muxes, scalable and parameterized — the selection primitive behind every datapath.
Beginner~40 minSelf-checking testbench2 challenges
Concepts covered
- Selection logic
- case vs assign
- Parameterized width
This lab is part of Verilog HDL Labs
Unlock the complete lab — detailed explanation, functional spec, starter and full DUT code, a commented self-checking testbench, expected outputs, waveform walkthrough, solutions and challenges — with the Verilog HDL Labs package. Use the card to get access.
- Detailed explanation & spec
- Complete Verilog DUT code
- Self-checking testbench
- Expected outputs & waveforms
- Solutions & debugging help
- 2 progressive challenges