SystemVerilog · Topic
SystemVerilog Tasks & Functions
Tasks, functions, automatic versus static lifetime, arguments, return values and void functions — the subroutine rules that decide reuse and re-entrancy.
The distinction that matters is not syntax but time: a function cannot consume simulation time, and a task can. Everything else follows — a function may be called from an expression, a task may not, and a task that blocks inside a loop changes when its caller resumes. The second trap is lifetime: a static task shares its locals across every concurrent call, so two threads calling the same driver task corrupt each other's state in a way that looks like a race in the DUT.