GLS · Topic
Adapting an RTL Testbench for Gate-Level Simulation
Why an RTL testbench breaks at gate level — hierarchical references, force/release, zero-delay assumptions and checker timing.
An RTL testbench usually depends on things a netlist no longer has. Hierarchical references reach into signals synthesis renamed or optimised away; checkers sample at instants that were safe with zero delay and are not once delays are annotated; force and release target nets that no longer exist. Adapting the testbench is not a workaround — it is the work of making the check valid against the thing actually being shipped.