GLS · Topic
SDF Annotation — Back-Annotating Timing into Gate-Level Sim
Standard Delay Format annotation — what SDF contains, how it attaches to a netlist, and how to prove the annotation actually applied.
An SDF file carries the delays a timing tool computed so that a gate-level simulation can behave like the physical circuit rather than like a zero-delay abstraction. The failure that matters is silent: if the hierarchy path in the SDF does not match the instance path in the simulation, the annotation is skipped and the run continues at zero delay, looking healthy and proving nothing. Checking the annotation log is not optional.