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22Modules
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Coherency first, not packets
MSI / MESI / MOESI / MESIF before CHI opcodes — the mental model that turns CHI from cryptic to obvious. Every later module rides on these foundations.
Interview-ready depth
A dedicated interview module plus per-chapter interview weighting — RN vs HN, ReadUnique flow, deadlock-avoidance rules, credit mechanisms, coherency-bug debug.
Design → verify → debug
RTL pipelines (request / snoop / directory), distributed scoreboards, SVA, and waveform-based debugging — the full engineering loop for a coherent SoC.
AMBA CHI Complete Curriculum
Your Learning Roadmap
162 chapters · 22 modules — cache coherency, RN/HN/SN nodes, and distributed-directory fabrics.
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Module 1
Cache Coherency Foundations
1.1Why Cache Coherency ExistsPlanned1.2The Multi-Core ProblemPlanned1.3Shared Memory SystemsPlanned1.4Cache Hierarchy ReviewPlanned1.5The Stale Data ProblemPlanned1.6The Write Visibility ProblemPlanned1.7The Read Visibility ProblemPlanned1.8Why AXI Is Not EnoughPlanned1.9Introduction to CoherencyPlanned
Module 2
Coherency Protocol Foundations
2.1MSI ProtocolPlanned2.2MESI ProtocolPlanned2.3MOESI ProtocolPlanned2.4MESIF ProtocolPlanned2.5The Ownership ConceptPlanned2.6The Dirty Data ConceptPlanned2.7InvalidationsPlanned2.8Snoop MechanismsPlanned2.9Reading State-Transition TablesPlanned2.10Real Coherency ExamplesPlanned
Module 3
Why CHI Exists
3.1Evolution of AMBAPlanned3.2AHB Recap (for CHI Context)Planned3.3AXI Recap (for CHI Context)Planned3.4ACE IntroductionPlanned3.5ACE LimitationsPlanned3.6Scalability ChallengesPlanned3.7Coherent FabricsPlanned3.8Why CHI Was CreatedPlanned
Module 4
CHI Architecture Overview
4.1The CHI Mental ModelPlanned4.2The Request Node (RN)Planned4.3The Home Node (HN)Planned4.4The Slave Node (SN)Planned4.5Fully Distributed ArchitecturePlanned4.6Point-to-Point LinksPlanned4.7Packet-Based DesignPlanned4.8Layered ArchitecturePlanned
Module 5
CHI System Components
5.1RN-F (Fully Coherent Request Node)Planned5.2RN-D (IO-Coherent Request Node)Planned5.3HN-F (Fully Coherent Home Node)Planned5.4HN-I (IO Home Node)Planned5.5SN-F (Fully Coherent Slave Node)Planned5.6SN-I (IO Slave Node)Planned5.7Cache AgentsPlanned5.8Memory Controllers in CHIPlanned5.9The Interconnect FabricPlanned
Module 6
CHI Channels
6.1The Four CHI ChannelsPlanned6.2The Request Channel (REQ)Planned6.3The Response Channel (RSP)Planned6.4The Data Channel (DAT)Planned6.5The Snoop Channel (SNP)Planned6.6Packet Common FieldsPlanned6.7Channel Routing & TopologyPlanned
Module 7
CHI Transaction Model
7.1The Read TransactionPlanned7.2The Write TransactionPlanned7.3The Atomic TransactionPlanned7.4The Snoop TransactionPlanned7.5Transaction LifecyclePlanned7.6The Transaction State MachinePlanned
Module 8
Request Flows
8.1ReadShared FlowPlanned8.2ReadUnique FlowPlanned8.3ReadClean FlowPlanned8.4ReadNotSharedDirty FlowPlanned8.5WriteUnique FlowPlanned8.6WriteBack FlowPlanned8.7Evict FlowPlanned8.8MakeUnique FlowPlanned
Module 9
Snoop Flows
9.1Why Snoops ExistPlanned9.2Snoop Request TypesPlanned9.3Snoop ResponsesPlanned9.4Snoop-Driven InvalidationPlanned9.5Snoop Data TransferPlanned9.6Snoop Ownership TransferPlanned9.7Snoop ForwardingPlanned
Module 10
Cache State Management
10.1The CHI Cache StatesPlanned10.2State TransitionsPlanned10.3Ownership in CHIPlanned10.4Sharing in CHIPlanned10.5Dirty Data HandlingPlanned10.6The CHI State TablesPlanned10.7Common State BugsPlanned
Module 11
Directory-Based Coherency
11.1Centralised DirectoryPlanned11.2Distributed DirectoryPlanned11.3Sharer TrackingPlanned11.4Owner TrackingPlanned11.5Directory Scalability BenefitsPlanned11.6The CHI Directory ModelPlanned
Module 12
Ordering and Consistency
12.1Memory OrderingPlanned12.2Transaction OrderingPlanned12.3Barrier TransactionsPlanned12.4DMB SemanticsPlanned12.5DSB SemanticsPlanned12.6CHI Ordering RulesPlanned12.7Consistency ModelsPlanned
Module 13
CHI Data Transfers
13.1Data PacketsPlanned13.2Data SourcesPlanned13.3Data SinksPlanned13.4Forwarded DataPlanned13.5Memory DataPlanned13.6Cache DataPlanned13.7Data IntegrityPlanned
Module 14
CHI Flow Control
14.1The Credit MechanismPlanned14.2Link Flow ControlPlanned14.3Deadlock AvoidancePlanned14.4BackpressurePlanned14.5Congestion HandlingPlanned14.6Throughput OptimisationPlanned
Module 15
CHI Performance
15.1CHI Latency AnatomyPlanned15.2CHI ThroughputPlanned15.3ScalabilityPlanned15.4Multi-Core ScalingPlanned15.5Directory EfficiencyPlanned15.6Snoop ReductionPlanned15.7Fabric UtilisationPlanned
Module 16
CHI RTL Design Thinking
16.1Request ProcessingPlanned16.2Snoop ProcessingPlanned16.3Directory ManagementPlanned16.4Cache ControllersPlanned16.5Transaction TrackingPlanned16.6Outstanding RequestsPlanned
Module 17
CHI Verification
17.1Protocol VerificationPlanned17.2Coherency VerificationPlanned17.3CHI ScoreboardsPlanned17.4Reference ModelsPlanned17.5CHI AssertionsPlanned17.6CHI Functional CoveragePlanned17.7UVM Architecture for CHIPlanned
Module 18
CHI Debugging
18.1Lost OwnershipPlanned18.2Incorrect State TransitionPlanned18.3Missing SnoopPlanned18.4Data CorruptionPlanned18.5Directory CorruptionPlanned18.6DeadlockPlanned18.7Credit IssuesPlanned18.8Ordering ViolationsPlanned
Module 19
CHI Interview Mastery
19.1What Is CHI?Planned19.2Beginner RN / HN / SN QuestionsPlanned19.3RN vs HN QuestionPlanned19.4Directory Role QuestionPlanned19.5Ownership Transfer QuestionPlanned19.6ReadUnique Flow QuestionPlanned19.7Deadlock Avoidance QuestionPlanned19.8Credit Mechanism QuestionPlanned19.9Coherency Bug Debug QuestionPlanned19.10Large SoC Architecture QuestionPlanned
Module 20
Real Industry Case Studies
20.1Mobile SoCsPlanned20.2AI AcceleratorsPlanned20.3CPU ClustersPlanned20.4Cache-Coherent DMAPlanned20.5Multi-Core SubsystemsPlanned20.6Server-Class ProcessorsPlanned
Module 21
CHI Design-Review Checklist
21.1Architecture Review ChecklistPlanned21.2RTL Review ChecklistPlanned21.3Verification Review ChecklistPlanned21.4Performance Review ChecklistPlanned21.5Debug Review ChecklistPlanned21.6Interview Review ChecklistPlanned
Module 22
CHI Misconceptions Engineers Have
22.1“CHI Is Just AXI With Coherency”Planned22.2“Snooping Scales Forever”Planned22.3“Directory Means No Snoops”Planned22.4“Coherency Guarantees Ordering”Planned22.5“ReadUnique Always Fetches Data”Planned22.6“CHI Is Only For Arm CPUs”Planned22.7“Snoop Filters Are Always Perfect”Planned