Case Study — Mini-SoC GLS Signoff Flow

Chapter 14 · Section 14.6 · Industry Case Studies

Project thread — this completes the thread: the single flip-flop (14.1), grown through counter/FSM/peripherals, is now a mini-SoC at clean-GLS signoff. Chapter 15 prepares you to talk GLS (interview/signoff review).

1. Why Should I Learn This?

This is everything at once — the clean-GLS signoff of a real chip, integrating the whole book.

• All per-block bars + integration + power/DFT/CDC at the system level.
• Run tiered (13.4), auto-triaged (13.5), alongside LEC/STA/static CDC.
• Catches integration bugs only SoC-level GLS sees (e.g. isolation leak to the bus, 10.6).

It's the destination the whole project thread was building toward.

2. Real Silicon Story — the SoC that hung when a domain slept

A mini-SoC passed every block's GLS individually, but at the system level it hung whenever a peripheral domain powered down to save energy.

The powered-down domain's output fed the always-on bus with no isolation (10.6/10.3), so its corruption X leaked onto the bus and hung the CPU — an integration bug no single-block run could catch (each block was fine alone). SoC-level GLS — power-aware, with the domains switching — surfaced it; adding isolation (asserted before power-down) fixed it.

Lesson: a SoC has integration bugs no block-level run catches — a powered-down domain leaking onto the bus, a cross-block CDC glitch, a scan/power interaction. SoC-level GLS signoff (power-aware, all blocks, tiered) is what catches them before tape-out.

3. Concept — the mini-SoC signoff flow

The design: the mini-SoC — CPU + bus + peripherals (the earlier case designs integrated), with power domains, DFT/scan, and clock-domain crossings.

The clean-GLS SoC signoff gate — the sum of everything:

• All per-block bars — function sanity, full-timing clean (14.2), X/reset clean (14.3), clock-gate (14.4), handshake/read-data (14.5).
• Integration — blocks working together (bus transactions across peripherals, CPU control).
• System-level concerns:
  • Power (Chapter 10): domains switch off (corruption), isolation clamps (no bus leak), retention preserves state, sequencing correct (isolate→save→off; on→restore→de-isolate).
  • DFT/scan (Chapter 11): scan chains intact, patterns simulate, test-mode reset/X.
  • CDC (Chapter 9): crossings synchronized (+ static CDC/MTBF), no cross-block reconvergence glitch.

Run it as a pipeline (Chapter 13):

• Tiered (13.4): zero-delay functional nightly (subset), timed at milestones, a full clean run gating tape-out.
• Auto-triaged (13.5): known-expected Xs classified away (justified), new surfaced; first-divergence auto-detected.
• Alongside signoffs (13.4): LEC (equivalence), STA (timing), static CDC — GLS is one gate.

Clean-GLS SoC signoff (the gate):

• No unexplained X, no real violations, verified SDF, power/DFT/CDC clean, integration clean — reviewed with LEC/STA/static CDC.

Scope (accuracy):

• Clean-GLS signoff is one gate among several (LEC/STA/static-CDC/UVM, 13.4) — GLS is the dynamic gate-level input; it stays dynamic (0.3).

4. Mental Model — the finished building, inspected as a whole

The mini-SoC is the finished building — every room (block) inspected individually (14.1–14.5), now inspected as a whole.

• Room-by-room passing (per-block bars) is necessary but not sufficient — the building can still fail on how rooms interact: the power grid across floors (a sleeping wing leaking onto the main line — isolation, 10.6), the intercom between floors on different schedules (CDC), the building-wide test wiring (scan).
• You inspect the whole building (SoC-level GLS) — power-aware (flip breakers on real floors), with all systems live — and you do it continuously (tiered) with an automated inspector (triage) that flags only new issues.
• And the building inspection (GLS) is one of several sign-offs — the structural engineer (STA), the blueprint auditor (LEC), the crossings inspector (static CDC) all sign too.

Rooms pass individually and the whole building passes as a system — that's the SoC signoff.

5. Working Example — the mini-SoC signoff package

The integration and the signoff flow (tool-neutral):

# Mini-SoC — REPRESENTATIVE integration (the project thread, assembled):
#   cpu  +  axi bus  +  peripherals { uart/timer (14.4), axi-lite regs (14.5), counter (14.2), fsm (14.3) }
#   + power domains (Ch10)  + DFT/scan (Ch11)  + clock-domain crossings (Ch9)

# Mini-SoC GLS signoff gate — REPRESENTATIVE (the sum of the whole book):
# PER-BLOCK BARS (14.1-14.5):  function sanity | full-timing (verified SDF, 4.5/14.2) | X/reset (14.3)
#                              | clock-gate enable (14.4) | handshake/read-data (14.5)
# INTEGRATION:                 cross-block bus transactions; CPU controls peripherals
# POWER (Ch10):                domains switch off (corrupt) -> ISOLATION clamps (no bus leak) ->
#                              RETENTION preserves -> SEQUENCING (isolate->save->off; on->restore->de-iso)
# DFT/SCAN (Ch11):             chains intact; patterns simulate; test-mode reset/X
# CDC (Ch9):                   crossings synchronized (+ static CDC/MTBF); no cross-block reconvergence glitch
# PIPELINE (Ch13):             TIERED (nightly zero-delay / milestone timed / clean gate, 13.4)
#                              AUTO-TRIAGED (known classified away, NEW surfaced, 13.5)
#                              ALONGSIDE LEC | STA | static CDC (GLS = one gate, 13.4)
# CLEAN-GLS SIGNOFF: no unexplained X + no real violations + power/DFT/CDC/integration clean

Practical context (representative, tool-neutral):

gls/case_soc/
  netlist/soc.vg  upf/soc.upf(Ch10)  sdf/soc.sdf(Ch4)  patterns/atpg(Ch11)  tb/  expected/  waivers/(13.5)
# Flow: integrate -> tiered GLS (nightly zero-delay / milestone timed / clean gate, 13.4)
#       -> auto-triage (13.5) -> review WITH LEC/STA/static CDC (13.4) -> clean-GLS signoff -> tape-out
# Clean-GLS signoff = all per-block bars + integration + power/DFT/CDC clean, no unexplained X, no real violations.

The mini-SoC bring-up (power/reset/clock/domains), as a real waveform:

6. Debugging Session — an integration bug only SoC-level GLS catches

7. Common Mistakes

• Assuming per-block passing means the SoC passes. Integration bugs need SoC-level GLS.
• Not running power-aware SoC GLS — misses isolation leaks / sequencing (10.6).
• Running the SoC only at the end — tier it (13.4); auto-triage (13.5).
• Treating clean-GLS signoff as the only gate. It's one among LEC/STA/static CDC (13.4).
• Not verifying the combined gate (all bars + integration + power/DFT/CDC).

8. Industry Best Practices

• Run SoC-level, power-aware GLS (domains switching, all blocks integrated).
• Tier it (nightly zero-delay / milestone timed / clean gate, 13.4) and auto-triage (13.5).
• Review the clean-GLS gate alongside LEC/STA/static CDC (13.4).
• Verify the combined gate — all per-block bars + integration + power/DFT/CDC clean.
• Catch integration bugs (isolation leaks, cross-block CDC, scan/power) at the SoC level.

Senior Engineer Thinking

• Beginner: "Every block's GLS passed, so the SoC is clean."
• Senior: "Block-clean isn't SoC-clean — integration bugs (a sleeping domain leaking onto the bus, a cross-block CDC glitch) need SoC-level power-aware GLS, run tiered and auto-triaged, alongside LEC/STA/static CDC. Clean-GLS signoff sums all the bars plus integration plus power/DFT/CDC."

The senior runs SoC-level power-aware GLS for integration bugs and treats clean-GLS as one gate among several.

Silicon Impact

The mini-SoC case is the destination — the clean-GLS signoff of a real chip — and it makes the book's thesis concrete: GLS catches what nothing else does, at every scale, culminating in integration bugs only SoC-level GLS sees. A powered-down domain leaking onto the bus (missing isolation), a cross-block CDC reconvergence glitch, a scan/power interaction, a reset-sequencing error — each is invisible to block-level runs and to LEC/STA/static CDC (topology/timing/structure), and each is a catastrophic, power-or-mode-triggered silicon failure (0.3) if it ships. SoC-level, power-aware, tiered, auto-triaged GLS — reviewed alongside LEC/STA/static CDC — is the one gate that catches them, and the clean-GLS signoff (all per-block bars + integration + power/DFT/CDC, no unexplained X, no real violations, verified SDF) is what says the netlist is ready to tape out. From a single flip-flop (14.1) to this — the whole discipline, applied to a chip.

Engineering Checklist

• Ran SoC-level, power-aware GLS (domains switching, blocks integrated).
• Verified all per-block bars + integration + power/DFT/CDC clean.
• Ran tiered (13.4) and auto-triaged (13.5).
• Reviewed the clean-GLS gate alongside LEC/STA/static CDC (13.4).
• Caught integration bugs (isolation leaks, cross-block CDC, scan/power) at the SoC level.

Try Yourself

1. Integrate the case designs into a mini-SoC with power domains and run SoC-level power-aware GLS.
2. Observe: power a peripheral domain down with its bus-facing output un-isolated — corruption leaks onto the bus and hangs the CPU (an integration bug, 10.6).
3. Change: add isolation (asserted before power-down, correct sequence, 10.3/10.5).
4. Expect: the bus stays clean when the domain sleeps. Then verify the full clean-GLS gate — all bars + integration + power/DFT/CDC — run tiered and auto-triaged, alongside LEC/STA/static CDC. You've signed off a chip.

Any free Verilog simulator (power-aware where available) demonstrates the SoC integration case; the flow is tool-independent. No paid tool required for the concept.

Interview Perspective

• Weak: "If every block's GLS passes, the SoC is done."
• Good: "The SoC needs its own GLS — integration and power behavior aren't visible at the block level."
• Senior: "Clean-GLS SoC signoff sums every per-block bar (function/timing/X-reset/clock-gate/handshake) plus integration plus power/DFT/CDC — run tiered (nightly zero-delay / milestone timed / clean gate), auto-triaged (known classified away, new surfaced), and reviewed alongside LEC/STA/static CDC as one gate. SoC-level power-aware GLS catches integration bugs no block run can — a sleeping domain leaking onto the bus, a cross-block CDC glitch, a scan/power interaction. That's the whole discipline, applied to a chip."

9. Interview / Review Questions

10. Key Takeaways

• The mini-SoC case is the grand capstone — the earlier designs (DFF/counter/FSM/UART/AXI) integrated into a CPU + bus + peripherals, taken through a full clean-GLS signoff, completing the project thread from a single flip-flop to a chip.
• Clean-GLS SoC signoff sums everything: all per-block bars (function/full-timing/X-reset/clock-gate/handshake) + integration (blocks together) + system concerns — power (isolation/retention/sequencing, Ch10), DFT/scan (Ch11), CDC (Ch9).
• Run it as a pipeline (Ch13): tiered (nightly zero-delay / milestone timed / clean gate, 13.4), auto-triaged (known classified away, new surfaced, 13.5), alongside LEC/STA/static CDC — GLS is one gate.
• SoC-level, power-aware GLS catches integration bugs no block-level run can — a powered-down domain leaking onto the bus (missing isolation, 10.6), a cross-block CDC glitch (9.5), a scan/power interaction — each invisible to block runs and to LEC/STA/static CDC.
• Clean-GLS signoff = all bars + integration + power/DFT/CDC clean, no unexplained X, no real violations, verified SDF — one gate among several, saying the netlist is ready to tape out. This integrates the whole book; GLS is the dynamic gate-level input (0.3/13.4). Next: Chapter 15 — interview & signoff review preparation.

Quick Revision

Mini-SoC case = GRAND CAPSTONE (whole book). Integrate DFF/counter/FSM/UART/AXI → CPU+bus+peripherals. Clean-GLS signoff = all per-block bars + integration + power (Ch10) / DFT (Ch11) / CDC (Ch9), no unexplained X, no real violations, verified SDF. Run tiered (13.4) + auto-triaged (13.5), alongside LEC/STA/static CDC (one gate). SoC-level power-aware GLS catches integration bugs no block run can (isolation leak to bus 10.6, cross-block CDC 9.5, scan/power). Completes the thread: flip-flop → chip. Next: Chapter 15 — interview & signoff review prep.