Case Study — AXI-Lite Peripheral GLS

Chapter 14 · Section 14.5 · Industry Case Studies

Project thread — the UART/timer (14.4) becomes an AXI-Lite bus peripheral here. 14.6 integrates all the peripherals into the mini-SoC signoff.

1. Why Should I Learn This?

A bus peripheral adds protocol handshakes and read-data timing to the GLS picture.

• Prior bars: functional sanity + full-timing (14.2) + X/reset (14.3).
• Bus-specific: handshake + read-data path must meet timing under real delays.
• The debug: a slow read-data path violating setup at capture (8.2), triaged (8.4).

This is the last single-block case before the SoC integration (14.6).

2. Real Silicon Story — the AXI read that returned stale data

An AXI-Lite peripheral passed functional GLS but, under SDF timing, the master occasionally captured stale read data.

The read-data path (register file → read mux → rdata) was too slow at the slow corner — it violated setup at the master's capture flop (a real long-path setup, 8.2). Functional (zero-delay) GLS couldn't see it; the timed run did. It was not a testbench sampling artifact (5.4) — STA confirmed the real path. Pipelining the read path fixed it.

Lesson: a bus peripheral's read-data path must meet timing — a slow read path violates setup at the master's capture, a real timing bug the timed run catches (and STA confirms). Triage it real-vs-artifact; don't dismiss it.

3. Concept — the AXI-Lite peripheral case

The design: an AXI-Lite register-file peripheral — valid/ready handshakes, address decode, register file, read/write channels.

AXI-Lite GLS combines the bars:

• Functional sanity — a few read/write transactions confirm the block works at the gate level (equivalence sanity, 13.3). Full protocol coverage/compliance is RTL/UVM/VIP + formal's job, not GLS.
• Full-timing clean (14.2) — verified SDF + no real violations + no unexplained X.
• X/reset clean (14.3) — registers reset, no power-up X on the bus outputs.

The bus-specific concern — handshake & read-data timing:

• Under real delays, the valid/ready handshake and the read-data path must meet timing.
• A slow read-data path (register file → read mux → rdata) can violate setup at the master's capture (a real long-path setup, 8.2), worst at the slow corner (3.4).
• A testbench sampling the handshake/read data at the edge (5.4) can create a false mismatch — triage real-vs-artifact (8.4).

AXI-clean (the combined bar):

• Functional sanity passes, full-timing clean, X/reset clean, handshake & read-data meet timing (real path issues fixed; artifacts triaged).

Scope (accuracy):

• GLS spot-checks the block; protocol compliance/coverage = RTL/UVM/VIP/formal; timing signoff = STA (0.3). GLS stays dynamic.

4. Mental Model — a service window with a conversation and a deadline

The AXI-Lite peripheral is a service window (the bus interface) with a conversation protocol (valid/ready) and a deadline (timing).

• The conversation (handshake) must follow the rules — but whether the content is right (full protocol compliance) is checked by the rulebook inspectors (RTL/UVM/VIP/formal), not this window.
• What this window (GLS) checks is that the conversation physically happens on time under real delays — especially that when the master asks to read, the data comes back fast enough to be captured before the deadline (setup at the master's capture, 8.2).
• A slow clerk (a slow read-data path) hands the data over too late → the master grabs stale data (setup violation) — a real timing bug, worst on a bad day (slow corner).
• And you must not confuse a real slow clerk with a camera that filmed too early (edge-sampling artifact, 5.4) — check whether it's real (STA).

The window checks the conversation happens on time (real delays); the rulebook (VIP/formal) checks the content.

5. Working Example — the AXI-Lite artifact set

The AXI-Lite peripheral (representative RTL sketch + the slow read path):

// AXI-Lite register-file peripheral (read channel) — REPRESENTATIVE sketch
always_ff @(posedge clk)
  if (!rst_n) rvalid <= 0;
  else if (arvalid && arready) begin
    rdata  <= regfile[araddr[ADDR_HI:2]];   // read: regfile -> read mux -> rdata (a long path if wide)
    rvalid <= 1;
  end else if (rready) rvalid <= 0;
// handshake: arvalid/arready, rvalid/rready. rdata must meet SETUP at the MASTER's capture (8.2).

# THE BUG (this case): the read-data path is too slow at the slow corner (8.2)
#   regfile[...] -> wide read mux -> rdata : long combinational path
#   at the SLOW corner (3.4), rdata arrives too late -> SETUP violation at the master's capture
#   -> master captures STALE read data. (functional/zero-delay GLS misses it; TIMED run catches it.)
# THE FIX: pipeline/register the read-data path (or relax the timing) -> meets setup. Confirm with STA.

# Expected log — REPRESENTATIVE (AXI-clean bars):
#   [X/reset]      registers reset; no power-up X on bus outputs (14.3)
#   [full-timing]  SDF verified 0 unmatched (14.2); real delays; checks triaged (8.4)
#   [handshake]    valid/ready handshake meets timing under real delays
#   [read-data]    BUG: slow read path -> setup at master capture (8.2) ; FIX: pipeline read path
#   [function]     a few read/write transactions pass (sanity, NOT full coverage -> RTL/UVM/VIP, 13.3)
#   result: AXI-CLEAN = all bars pass. Protocol compliance=formal/VIP; timing signoff=STA (0.3)

Practical context (representative, tool-neutral):

gls/case_axi/
  rtl/axi_lite_regs.v   netlist/axi.vg   sdf/axi.sdf   tb/tb_axi.v (a few R/W txns)   expected/axi.log
# Flow: synth -> GLS: function sanity (few txns) + full-timing (verify SDF) + X/reset + handshake/read-data timing
# AXI-clean: all bars pass. Protocol compliance/coverage -> RTL/UVM/VIP + formal (13.3). Timing signoff -> STA.

An AXI read: slow read-data (setup violation) vs pipelined (meets timing), as a real waveform:

6. Debugging Session — an AXI read that violates setup at capture

7. Common Mistakes

• Only running functional (zero-delay) GLS on a bus block — misses read-data setup (8.2); run timed.
• Dismissing the setup violation as a TB artifact without triage (8.4) — STA confirms real.
• Expecting GLS to do protocol compliance/coverage — that's RTL/UVM/VIP/formal (13.3).
• Dropping the earlier bars — function/full-timing/X-reset still apply.
• Not verifying SDF annotation on the timed run (4.5).

8. Industry Best Practices

• Run timed GLS on bus blocks — the read-data path is a slow-path setup risk (8.2).
• Triage handshake/read-data violations real-vs-artifact (8.4); confirm real with STA.
• Keep protocol compliance/coverage in RTL/UVM/VIP + formal (13.3).
• Verify the combined AXI-clean bar (function/timing/X-reset/handshake/read-data).
• Verify SDF annotation on the timed run (4.5); use the right corner (3.4).

Senior Engineer Thinking

• Beginner: "Functional GLS passed, so the AXI block is done."
• Senior: "Functional (zero-delay) misses read-data setup. Under timing, does rdata meet setup at the master's capture — especially the slow corner? A slow read path is a real setup bug (STA confirms) — pipeline it. Protocol compliance is VIP/formal's, not GLS's."

The senior runs timed GLS on the bus block, catches the read-data setup path, and keeps protocol compliance in VIP/formal.

Silicon Impact

A bus peripheral's read-data timing is a classic, high-impact silicon risk: a slow read-data path that violates setup at the master's capture returns stale/corrupt data on reads — a corner-dependent, intermittent bus failure (0.3) that functional (zero-delay) GLS cannot see. The timed GLS run (14.2's bar) is where it surfaces, and STA confirms it — a real design fix (pipeline the read path). The AXI-Lite case also draws a scope line that matters at SoC scale: GLS spot-checks the block's gate-level soundness (function sanity, timing, X/reset, handshake/read-data), while protocol compliance and coverage stay with RTL/UVM/VIP and formal (13.3) — running the full AXI protocol suite in GLS would be the 10–100× duplication mistake. AXI-clean is the last single-block bar before all the peripherals integrate into the mini-SoC (14.6).

Engineering Checklist

• Ran timed GLS on the bus block (read-data setup risk, 8.2).
• Triaged handshake/read-data violations real-vs-artifact (8.4); confirmed real with STA.
• Kept protocol compliance/coverage in RTL/UVM/VIP + formal (13.3).
• Verified full-timing clean (SDF verified, 14.2) and X/reset clean (14.3).
• Confirmed AXI-clean = function sanity + full-timing + X/reset + handshake/read-data timing.

Try Yourself

1. Build an AXI-Lite register-file peripheral with a wide, unpipelined read mux; run timed GLS at the slow corner.
2. Observe: on a read, rdata arrives too late — a setup violation at the master's capture (stale data, 8.2).
3. Change: pipeline the read-data path so it meets setup; confirm with STA.
4. Expect: the read returns correct data in time. Then run functional (zero-delay) GLS and confirm it missed the setup bug — proving the timed run's value. Keep protocol coverage in VIP/formal.

Any free Verilog simulator with SDF runs the AXI-Lite timing case. No paid tool required for the concept.

Interview Perspective

• Weak: "The AXI block passed functional GLS, so it's timed-clean too."
• Good: "Functional GLS misses timing — under SDF, the read-data path must meet setup at the master's capture."
• Senior: "A bus peripheral's read-data path (regfile → read mux → rdata) is a slow-path setup risk at the slow corner — the timed GLS run catches it, STA confirms it, and I pipeline the read path. I triage real-vs-artifact so I don't confuse it with a TB edge-sample. And protocol compliance/coverage is RTL/UVM/VIP + formal's job — GLS spot-checks the block's gate-level soundness, it doesn't run the protocol suite."

9. Interview / Review Questions

10. Key Takeaways

• An AXI-Lite register-file peripheral brings a bus protocol to GLS — valid/ready handshakes, address decode, register file, read/write channels.
• AXI-Lite GLS combines the earlier bars — functional sanity (a few read/write transactions, not full coverage, 13.3), full-timing clean (14.2), X/reset clean (14.3) — with the bus-specific concern: handshake & read-data timing under real delays.
• The classic bug: a slow read-data path (register file → read mux → rdata) violates setup at the master's capture, worst at the slow corner — a real timing path (8.2) the timed run catches and STA confirms; triage real-vs-artifact (8.4).
• AXI-clean = function sanity + full-timing + X/reset + handshake/read-data timing — with protocol compliance/coverage owned by RTL/UVM/VIP + formal, and timing signoff by STA (0.3).
• GLS spot-checks the block's gate-level soundness — it doesn't run the protocol suite; the last single-block bar before the mini-SoC integration (14.6). GLS stays dynamic. Next: 14.6 — mini-SoC GLS signoff flow.

Quick Revision

AXI-Lite case = bus peripheral GLS. Combines earlier bars — functional sanity (few txns) + full-timing (14.2) + X/reset (14.3) — plus the bus-specific concern: handshake & read-data timing under real delays. Classic bug: slow read-data path → SETUP violation at the master's capture (real, 8.2, slow corner), triaged real-vs-artifact (8.4), STA confirms → pipeline the read path. Protocol compliance/coverage = RTL/UVM/VIP + formal (13.3), not GLS. AXI-clean = all bars pass. Next: 14.6 — mini-SoC GLS signoff flow.