DFT · Chapter 2 · Fault Models
Bridging & IDDQ Faults
Stuck-at models a node frozen to a rail and transition models a node that is too slow, but many real defects are shorts between two signal nodes. A bridging fault represents two nodes shorted together, and its behavior depends on relative drive strength: it can act as a wired-AND pulling toward zero, a wired-OR pulling toward one, or dominant where the stronger driver wins. Realistic bridges occur between adjacent nets, so the node pairs are extracted from layout. IDDQ testing measures the quiescent supply current, since a defect-free static CMOS circuit draws almost no static current while a short or leak draws elevated current, so the defect is caught by measuring current instead of a logic value. IDDQ is powerful for shorts logic tests miss, but modern high background leakage erodes its signal-to-noise and it is slow, pushing the industry toward delta-IDDQ and statistical methods.
Intermediate14 min readDFTBridging FaultIDDQLeakageLayout-Aware
Chapter 2 · Section 2.4 · Fault Models
Project thread — 2.2/2.3 tested the counter's nodes for stuck and slow; here we test for shorts between bits (bridging) and detect them by quiescent current (IDDQ).
1. Why Should I Learn This?
Shorts between signals and leakage are a real defect class that stuck-at and transition miss — bridging and IDDQ target them.
- Bridging: two nodes shorted → wired-AND / wired-OR / dominant; layout-dependent, extracted from adjacency.
- IDDQ: measure quiescent supply current — a short/leak draws elevated current; detect by current, not logic.
- IDDQ is powerful but eroded by modern high leakage → delta-IDDQ / statistical; it's slow (current must settle).
2. Real Silicon Story — the short that logic tests waved through
A part with strong stuck-at and transition coverage still had a stubborn DPPM tail. Failure analysis kept finding shorts between adjacent metal lines — two signal nets bridged by a sliver of metal.
The logic tests often passed these parts: whenever the two bridged nets happened to hold the same value, the short did nothing observable, and the specific pattern that drove them to opposite values and propagated the corruption was rarely generated by a stuck-at-targeted flow. But every one of those bridged dies drew elevated quiescent current — because the short is a conducting path in the otherwise-static CMOS.
Adding IDDQ measurements (and layout-extracted bridging targets) caught the tail: the bridged dies failed the current threshold even when logic passed. Lesson: shorts and leakage need their own models — bridging (opposite-value + propagate) and IDDQ (measure current, not logic) — because stuck-at/transition can't reliably see them.
3. Factory Perspective — how each role reads bridging/IDDQ
- What the test engineer sees: a layout-extracted bridging fault list and an IDDQ test flow with current thresholds (increasingly delta/statistical), plus the slow settling that limits IDDQ pattern count.
- What the yield engineer sees: current-signature data and spatial short clusters — pointing at process/lithography issues (adjacent-net shorts, particles) and driving failure analysis.
- What the RTL/DV engineer sees: less direct, but congested/adjacent routing of their signals raises bridge likelihood — and any logic that keeps nets in known static states helps IDDQ.
- What management cares about: IDDQ historically bought very low DPPM cheaply — but its erosion in modern leaky processes is a quality-vs-process decision affecting the DPPM plan (1.5).
4. Concept — bridging behavior, layout dependence, IDDQ
Bridging fault — two signal nodes shorted:
- Not node-to-rail (that's stuck-at) — a short between two signals.
- Behavior depends on relative drive:
- Wired-AND: the bridged pair resolves toward 0 when either driver pulls low.
- Wired-OR: resolves toward 1 when either pulls high.
- Dominant: the stronger driver wins and forces its value onto the weaker node.
- Detection: a pattern that sets the two nodes to opposite intended values (so the short actually corrupts one) and propagates the corrupted node to an observable point.
Why bridging is harder — layout dependence:
- Realistic bridges occur between physically adjacent nets, so you extract candidate pairs from layout (adjacency/coupling), not all possible pairs.
- Testing all N-squared node pairs is infeasible and unrealistic — layout extraction gives the few thousands of plausible pairs.
IDDQ — detect defects by current, not logic:
- Put the circuit in a static (quiescent) state and let it settle.
- A defect-free static CMOS gate draws ~0 static current (no DC path from VDD to GND) — only tiny leakage.
- A short / bridge / gate-oxide defect creates a conducting path → elevated IDDQ → detect by measuring supply current against a threshold.
- Strength: catches any conducting defect, including shorts a logic test never sensitized — powerful, historically very low DPPM.
IDDQ's real limitation (be precise):
- In deep-submicron processes, background leakage is large — the defect current can be smaller than the chip-to-chip leakage variation, so a single global threshold loses signal-to-noise.
- Industry response: delta-IDDQ (compare successive measurements on the same die), current-signature analysis, and statistical/outlier methods.
- IDDQ is slow — the current must settle before each measurement — so you take relatively few IDDQ measurements (not thousands).
IDDQ flips the whole strategy — measure current, not logic:
5. Mental Model — a hidden water leak in a shut-off house
Stuck-at/transition watch the taps (logic values). Bridging/IDDQ hunt a hidden pipe leak.
- A bridge is a cross-connection between two pipes that were meant to be separate. If both pipes carry the same pressure (A=B), you notice nothing — you must create a pressure difference (drive A≠B) to make the cross-leak show, then watch a downstream faucet (propagate).
- IDDQ is reading the master water meter with every tap shut off (quiescent). A perfect house uses ~0 water when idle; any hidden leak makes the meter creep — you detect it by the meter, not by any single faucet.
- The modern-leakage problem: if the whole neighborhood's pipes sweat a little (background leakage), a small leak is lost in the normal drip — so you compare this house to itself over time (delta-IDDQ) instead of one absolute number.
- Reading the meter takes time to settle, so you take few readings.
You catch a hidden cross-leak by forcing a pressure difference (bridging test) or by watching the idle meter (IDDQ) — not by staring at taps.
6. Working Example — a bridge between counter bits + IDDQ spike
Target a bridge between two adjacent counter outputs, then catch it two ways:
# Bridging detection — REPRESENTATIVE, SIMPLIFIED, tool-neutral:
# Suppose layout extraction flags count[1] and count[2] as ADJACENT -> candidate BRIDGE (wired-AND assumed).
# INVISIBLE case : a state with count[1]=count[2] (both 0 or both 1) -> short does nothing -> logic PASS
# DETECT case : drive count[1]=1, count[2]=0 (OPPOSITE) -> wired-AND pulls the pair toward 0
# -> count[1] corrupted 1->0 -> PROPAGATE count[1] to an observable point -> MISMATCH -> DETECTED
# Note: a stuck-at-targeted pattern set may rarely create the exact opposite-value + propagate condition -> escape risk.# IDDQ detection of the SAME bridge — REPRESENTATIVE:
# Put the counter in a settled static state where count[1] != count[2] (a conducting path through the bridge)
# Measure quiescent supply current:
# GOOD die : IDDQ ~ leakage floor (e.g. sub-microamp class, process-dependent)
# BRIDGED die: IDDQ ELEVATED (short conducts) -> exceeds threshold / delta -> FAIL
# Detection is by CURRENT -- no need to propagate a logic value to an output.
# Caveat: on a high-leakage process the elevated current may be small vs background -> use DELTA-IDDQ / statistical.7. Industry Flow — where bridging/IDDQ sit
They augment the logic-based tests, drawing on layout and current measurement:
8. Debugging Session — a DPPM tail that logic tests miss
A part with strong stuck-at and transition coverage still has a DPPM tail from adjacent-net shorts that logic tests only catch when a specific opposite-value-and-propagate pattern happens to exist; the fix is layout-extracted bridging targets plus IDDQ current measurement -- but on a modern high-leakage process a single IDDQ threshold fails, so use delta-IDDQ/statistical methods
SHORTS NEED OPPOSITE-VALUE+PROPAGATE OR CURRENT MEASUREMENT — NOT MORE STUCK-ATA part with high stuck-at and transition coverage still shows a persistent DPPM tail. Failure analysis repeatedly finds shorts between adjacent metal nets. Logic tests sometimes catch these, sometimes don't.
Adjacent-net shorts (bridging) are only visible to a logic test under a specific, rarely-guaranteed condition, and stuck-at-targeted patterns don't systematically create it. A bridge between nodes A and B does nothing observable whenever A and B hold the same value — the short just ties two equal nodes. It corrupts logic only when the pattern drives A and B to opposite values (so the wired-AND/OR/dominant behavior actually changes one node) and then propagates the corrupted node to an observable point. A pattern set generated to cover stuck-at faults has no reason to guarantee that exact opposite-value-plus-propagate condition on every layout-adjacent pair — so some bridged dies pass logic and escape. Meanwhile 'add more stuck-at patterns' doesn't help: bridging is a different fault model (pairwise, layout-dependent), not in the stuck-at list. And note IDDQ's own trap: on a modern high-leakage process, the bridge's extra current may be smaller than the die-to-die background leakage, so a single global IDDQ threshold produces false passes and false fails — the classic IDDQ 'signal lost in noise' problem.
Add layout-extracted bridging targets and IDDQ current measurement — and on modern nodes use delta/statistical IDDQ, not a single threshold. Extract plausible bridge pairs from layout adjacency and let ATPG generate patterns that drive each pair to opposite values and propagate the corruption — turning 'sometimes caught' into targeted coverage. In parallel, run IDDQ: place the circuit in static states (ideally ones that make suspected bridges conduct), let the current settle, and measure quiescent supply current — a bridged/leaky die draws elevated current and fails, even when logic passes. Because modern background leakage erodes a global threshold, compare each die to itself (delta-IDDQ) or use current-signature / statistical outlier analysis, and accept that IDDQ is slow (few measurements). The principle to lock in: bridging faults model node-to-node shorts (wired-AND/OR/dominant) that logic tests catch only under an opposite-value-and-propagate condition — so target realistic pairs from layout — while IDDQ detects any conducting defect (short, bridge, gate-oxide leak) by measuring quiescent supply current rather than a logic value, giving very low DPPM historically but requiring delta/statistical methods on modern high-leakage processes where a single current threshold no longer separates defect from background. (These augment, not replace, stuck-at (2.2) and transition (2.3); untestable faults are 2.5.)
9. Common Mistakes
- Thinking stuck-at covers shorts. A bridge is node-to-node, visible only under opposite-value + propagate — not guaranteed by stuck-at patterns.
- Testing all N-squared bridge pairs. Infeasible and unrealistic — extract layout-adjacent pairs only.
- Using a single global IDDQ threshold on a modern node. Background leakage swamps the defect — use delta/statistical IDDQ.
- Expecting many IDDQ measurements. Current must settle — IDDQ is slow, so measurements are few.
- Treating IDDQ as a logic test. It measures current, catching defects with no logic symptom at that state.
10. Industry Best Practices
- Extract bridge candidates from layout (adjacency/coupling) — realistic, tractable pairs.
- Generate opposite-value + propagate patterns for bridges — the only condition that makes them observable.
- Use IDDQ for shorts/leakage where process leakage permits — historically very low DPPM for those classes.
- On modern nodes, use delta-IDDQ / current-signature / statistical methods, not a single threshold.
- Budget IDDQ's slowness — settling limits pattern count; place measurements at high-value static states.
11. Senior Engineer Thinking
- Beginner: "Coverage is high — add more stuck-at patterns to kill the DPPM tail."
- Senior: "The tail is adjacent-net shorts — a different model. Stuck-at won't guarantee opposite-value + propagate on every bridge pair, so I extract pairs from layout and target them, and I add IDDQ to catch conducting defects by current. On this node the background leakage is high, so I use delta-IDDQ, not one threshold — and I accept IDDQ is slow."
The senior matches the model to the defect class and knows IDDQ's modern limits.
12. Silicon Impact
Bridging and IDDQ close a real, historically stubborn gap: node-to-node shorts and leakage that stuck-at and transition don't reliably catch. Bridging is important because shorts are a common physical defect (lithography, particles, adjacent-net coupling), and they're sneaky — invisible until a pattern makes the bridged pair take opposite values and propagates the corruption, which is why layout-extracted targeting matters. IDDQ was, for years, one of the highest-leverage tests in the industry: by measuring quiescent current it caught any conducting defect — including shorts with no logic symptom in the tested state — delivering very low DPPM for shorts/leakage at modest pattern count. Its decline is a genuine technology story: as processes shrank, background leakage grew until a single global threshold could no longer separate a defect's extra current from normal die-to-die variation — so IDDQ evolved into delta-IDDQ, current-signature, and statistical techniques rather than disappearing. For the RTL/DV and physical-design engineer, the connection is that routing congestion and adjacency raise bridge likelihood, and clean static states aid IDDQ — so floorplan and coding choices influence these defect classes' catchability. Net: to hit an aggressive DPPM (1.5), especially on older/mixed nodes or safety parts, bridging and IDDQ augment the stuck-at/transition backbone — you use the portfolio (2.1), not one model, to span the defect classes your process actually produces.
13. Engineering Checklist
- Extracted bridge candidate pairs from layout adjacency (not all pairs).
- Generated opposite-value + propagate patterns for bridging targets.
- Deployed IDDQ for shorts/leakage where process leakage permits value.
- Used delta-IDDQ / statistical methods on modern high-leakage nodes (not a single threshold).
- Budgeted IDDQ settling time (few measurements) and placed them at high-value states.
14. Try Yourself
- Assume layout flags counter bits count[1]/count[2] as adjacent → a wired-AND bridge candidate.
- Find an invisible state (count[1]=count[2]) and a detect state (opposite values) — show the short only acts in the second.
- Write the propagate step so the corrupted bit reaches an observable point.
- Describe the IDDQ detection of the same bridge: a static opposite-value state → elevated quiescent current → fail.
- Explain why a modern high-leakage process breaks a single IDDQ threshold, and name the fix (delta-IDDQ).
The reasoning is tool-neutral. Real bridge extraction comes from physical design; IDDQ needs an ATE current resource. Concepts here need no paid tool.
15. Interview Perspective
- Weak: "A bridging fault is a short, and IDDQ measures current."
- Good: "Bridging shorts two nodes (wired-AND/OR); IDDQ measures quiescent current to catch shorts/leaks logic tests miss."
- Senior: "A bridging fault shorts two signal nodes, behaving as wired-AND, wired-OR, or dominant by drive strength; it's invisible when the nodes match, so detection needs a pattern driving them opposite and propagating the corruption — and since realistic bridges are between adjacent nets, we extract pairs from layout, not test all N-squared. IDDQ attacks the same classes differently: in a static state, defect-free CMOS draws ~0 current, so a short/bridge/gate-oxide leak shows as elevated quiescent current — detection by current, not logic — historically very low DPPM. Its limit is modern leakage: background current swamps the defect, so we use delta-IDDQ/statistical methods, and it's slow (settling)."
16. Interview / Review Questions
17. Key Takeaways
- Bridging faults model two signal nodes shorted together — behaving as wired-AND, wired-OR, or dominant by relative drive — a class stuck-at (node-to-rail) and transition don't represent.
- Bridging is pairwise and layout-dependent: realistic shorts are between adjacent nets, so candidate pairs are extracted from layout (not all N-squared), and detection needs opposite values + propagate (the short is invisible when the nodes match).
- IDDQ testing detects any conducting defect (short, bridge, gate-oxide leak) by measuring quiescent supply current — defect-free static CMOS draws ~0, a defect draws elevated current — catching defects with no logic symptom in that state; historically very low DPPM.
- IDDQ's modern limitation: high background leakage erodes signal-to-noise, so a single global threshold fails → use delta-IDDQ / current-signature / statistical methods; IDDQ is also slow (current must settle) → few measurements.
- These models augment (not replace) stuck-at (2.2) and transition (2.3) — the portfolio (2.1) spans the defect classes your process produces, and floorplan/routing choices influence bridge likelihood. Next: 2.5 — why some faults are untestable.
18. Quick Revision
Bridging & IDDQ — shorts and leakage. BRIDGING = two SIGNAL nodes shorted → wired-AND / wired-OR / dominant (by drive). Invisible when the nodes MATCH → detect by driving them OPPOSITE + PROPAGATE. Layout-dependent → extract adjacent pairs, not all N². IDDQ = measure quiescent supply current: defect-free static CMOS ~0; a short/bridge/gate-oxide leak → ELEVATED current → detect by CURRENT, not logic (historically very low DPPM). Limit: modern high leakage swamps a single threshold → use delta-IDDQ / statistical; IDDQ is SLOW (settling). Augments stuck-at + transition. Next: 2.5 — untestable faults.