Working Example: ATPG on the FSM

Chapter 5 · Section 5.6 · ATPG — chapter capstone

Project thread — the full-scan FSM (4.5) is ATPG's target. This lesson generates its patterns and coverage, then hands the classified result to coverage closure (Chapter 6).

1. Why Should I Learn This?

This is Chapters 2–5 working together on one block — the concrete moment models + scan + ATPG become applied test.

• Input: DRC-clean full-scan FSM (4.5) + its stuck-at fault list (Ch2).
• Combinational ATPG (5.4): justify a state by loading it, propagate to a scan cell, generate the pattern (5.2).
• Fault-simulate to drop (5.3), compact, and classify faults (5.5).
• Output: a compact pattern set + coverage report — the input to signoff (Ch6).

2. Real Silicon Story — the whole flow paying off on one block

For a control block (an FSM much like the project's), a team had done everything right upstream: scan-ready RTL (4.1), clean insertion and DRC (4.2–4.4). When they finally ran ATPG, the payoff was immediate and undramatic — which is exactly what you want.

ATPG ran combinationally (full scan), justified each target state by loading it directly, propagated faults to scan cells, and fault-simulated to drop — reaching high coverage in minutes with a compact pattern set. The error-state transition fault that functional test could never reach was generated and detected by a single load-state/capture/observe pattern. The report showed mostly DETECTED, a handful of redundant/AU (accepted), and a few aborts that more effort recovered (5.5).

The lesson wasn't dramatic because the hard work was done in Chapters 3–4: a clean, scannable FSM makes ATPG easy. Lesson: ATPG on a well-prepared full-scan block is fast and high-coverage — the whole point of the preceding chapters — and it produces the classified coverage that signoff (Ch6) consumes.

3. Factory Perspective — the FSM ATPG run through each lens

• What the test engineer sees: a compact STIL pattern set + a coverage/fault-class report for the FSM — ready to sign off (Ch6) and hand to the ATE (1.3).
• What the yield engineer sees: that the FSM's next-state/output defects now fail the tester (binnable/diagnosable) — a failing pattern localizes the fault.
• What the RTL/DV engineer sees: that their scan-ready FSM (Ch4) yielded high coverage easily, and any AU faults point back to their controllability/observability (test points, Ch6).
• What management cares about: coverage + pattern count for the block — the DPPM contribution (1.5) and the test-time cost (1.4), both readable from this run.

4. Concept — running ATPG on the FSM, step by step

Setup (from Chapter 4):

• The full-scan FSM: state register → scan chain (scan_in → state[0..1] → scan_out), reset gated in test, DRC clean.
• The fault list (stuck-at, Ch2): faults on next-state logic, output logic, and the state register.

ATPG runs combinationally (5.4):

• Flops as pseudo-PI/PO — ATPG loads any current state and reads any next state via the chain.
• Per target fault: justify the required current state (load it) + inputs, propagate the fault effect to a scan cell (5.2), emit a load-state → capture → observe pattern.

Efficiency (5.3):

• Fault-simulate each pattern to drop every other fault it detects; random-fill the easy faults; compact the set.

Classify (5.5):

• Faults end as DT / RE / AU / AB; recover aborts with effort, accept redundant, test-point the fixable AU.

Concrete detection — the RUN→DONE next-state fault (from 4.5):

• Load RUN into the state scan chain (justify the current state directly — controllability).
• Set fin=1, capture one clock: good next-state logic → DONE; faulty (next-state term stuck) → stays RUN.
• Shift out and compare to golden DONE: faulty die → RUN ≠ DONE → detected.

Output: a compact pattern set (STIL) + a coverage/fault-class report → the input to Chapter 6.

The FSM's fault list becomes an applied pattern set:

5. Mental Model — the exam, written and administered for the FSM

Recall 5.1's exam analogy — here it's fully staged for the FSM.

• The syllabus is the FSM's fault list (every way its next-state/output logic could be wrong).
• ATPG (the exam-writer) uses the FSM's save/load (full scan) to write efficient questions: 'set the machine to RUN, apply fin, and check it reaches DONE.' Each question loads a state, takes one step, reads the result.
• It reuses questions ruthlessly (fault-sim dropping) so the exam is short, and it warms up with random questions to clear the easy material.
• The finished exam + answer key (patterns + golden) go to the proctor (the ATE, 1.3), who administers it to every die.
• The grade report (coverage + fault classes) tells you how much of the syllabus the exam covers — and which topics were impossible (redundant) or need a new question format (test points, Ch6).

The FSM's save/load (full scan) is what let the exam-writer ask 'from RUN, does fin reach DONE?' in one question instead of a playthrough.

6. Working Example — the FSM's ATPG patterns and report

A generated pattern and the run's report (the FSM is the tri-HDL design from 4.5):

# ATPG pattern detecting the RUN->DONE next-state fault — REPRESENTATIVE, SIMPLIFIED, tool-neutral:
# (FSM state encoding: IDLE=00, RUN=01, DONE=10, ERR=11 ; state chain: scan_in->state[0]->state[1]->scan_out)
  pattern 42:
    load_unload { chain = <shift in state = RUN (01)> ; }      # JUSTIFY current state = RUN (controllability)
    force_pi    { fin = 1 ; start=0; ack=0; clr=0 ; }          # set inputs
    capture     { ... one functional clock ... }               # next-state logic: RUN + fin -> DONE
    load_unload { chain = <expected state = DONE (10)> ; }     # GOLDEN next-state (observability)
#   GOOD die  : captured state = DONE (10) -> matches golden -> pass
#   FAULTY die: next-state term stuck -> captured state = RUN (01) -> scan_out != golden -> DETECTED
# The fault 4.5 called untestable functionally is DETECTED by loading RUN directly + observing DONE.

# ATPG report for the FSM — REPRESENTATIVE, SIMPLIFIED, tool-neutral:
  Design           : full-scan FSM (state reg -> scan chain, DRC clean)
  Fault model      : stuck-at (collapsed)
  Total faults     : 96
  Detected (DT)    : 92
  Redundant (RE)   :  2   (proven no pattern -> removed from denominator, 5.5)
  ATPG-untestable  :  1   (an unobservable output on an illegal state -> test point candidate, Ch6)
  Aborted (AB)     :  1   (raise effort -> recovers to DT)
  Patterns         : 14   (compact -> low shift/test time, 1.4)
  Test coverage    : ~98-99% (DT/(total-RE-AU))  -> hand to coverage closure (Ch6)
# Combinational (full scan) -> fast, high coverage. The ATE (1.3) applies the 14 patterns; coverage vs the MODEL (2.1).

The generated pattern, applied — good die passes, faulty die caught:

7. Industry Flow — the FSM run hands coverage to signoff

This ATPG run's output is exactly what coverage closure (Ch6) consumes:

8. Debugging Session — a next-state fault ATPG leaves undetected

9. Common Mistakes

• Blaming ATPG for an undetected FSM fault. It's a class (AB/AU/RE) — diagnose, don't tool-swap.
• Not recovering aborts. Raise effort — many aborts on the FSM are detectable (5.5).
• Ignoring illegal-state observability. An output only on an illegal state may be AU → add a test point (Ch6).
• Reading coverage as zero-defect. It's vs the stuck-at model (2.1) — add at-speed etc. as needed (2.3).
• Skipping chain integrity / DRC. Do both first (3.3, 4.3) or ATPG's golden is meaningless (4.3).

10. Industry Best Practices

• Feed ATPG a clean full-scan FSM (Ch4) — it makes ATPG combinational and fast (5.4).
• Use fault-sim dropping + random-fill + compaction for a compact set (5.3).
• Recover aborts, accept redundant, test-point AU (5.5, Ch6).
• Report test coverage and hand the classified result to signoff (Ch6).
• Hand STIL to the ATE — the tester applies/compares (1.3).

11. Senior Engineer Thinking

• Beginner: "ATPG left a fault undetected on the FSM — the tool's not good enough."
• Senior: "On a full-scan FSM, controllability is easy — an undetected fault is aborted (raise effort), AU (an unobservable illegal-state output → add a test point), or redundant (accept). I diagnose which (5.2/5.5), apply the matching fix, report test coverage, and pass it to signoff. ATPG did its job — I read the class."

The senior diagnoses the class, never tool-blames — the FSM's cleanliness makes ATPG's result trustworthy.

12. Silicon Impact

This capstone is the concrete payoff of Chapters 2–5: fault models (Ch2) define what to detect, scan (Ch3–4) makes the FSM's state controllable and observable, and ATPG (Ch5) turns that into applied test — a compact pattern set and a classified coverage report for a real control block. The reason it's fast and high-coverage is everything the prior chapters bought: because the FSM is full scan, ATPG runs combinationally (5.4), justifying any state by loading it and propagating faults to scan cells, so even a functionally-unreachable transition fault (the FSM's error-state edge) becomes a one-pattern load-state/capture/observe test — the exact defect that would have escaped functional test, now caught on the tester. The report is the deliverable that Chapter 6 signs off: coverage against the model, plus the fault classes (DT/RE/AU/AB) whose meanings (5.5) tell you the remaining moves — recover aborts with effort, test-point the AU (that unobservable illegal-state output), accept the redundant. Crucially, an undetected fault here is never 'ATPG failed' — it's a class the search produced, diagnosable by the controllability/observability reasoning of 5.2, which is what keeps closure rational instead of tool-blaming. For the RTL/DV engineer, the run validates the whole 'design for scan' investment: a clean, scan-ready FSM (Ch4) yields high coverage with a small pattern set — good for both DPPM (1.5) and test time (1.4) — and any residual AU points precisely at a testability improvement to make. That's the through-line of this course delivered on one block: from fault model to scan to ATPG to an applied, signed-off test, now ready for coverage closure in Chapter 6.

13. Engineering Checklist

• Ran combinational ATPG on the full-scan, DRC-clean FSM (Ch4/5.4).
• Generated a compact pattern set (fault-sim drop + random-fill + compaction, 5.3).
• Classified faults (DT/RE/AU/AB); recovered aborts, test-pointed AU, accepted redundant (5.5, Ch6).
• Confirmed the RUN→DONE (and other unreachable) faults are detected; reported test coverage.
• Handed the pattern set + classified coverage to signoff (Ch6) and STIL to the ATE (1.3).

14. Try Yourself

1. For the FSM, write the load-state/capture/observe pattern that detects the RUN→DONE next-state fault (load RUN, fin=1, expect DONE).
2. Show a faulty die (stuck next-state) yields RUN ≠ DONE → detected.
3. Sketch the ATPG report: patterns, coverage, and a few DT/RE/AU/AB faults.
4. Take an undetected FSM fault and decide its class (aborted/AU/redundant) and the fix (effort/test point/accept).
5. Explain why the FSM being full scan made this ATPG combinational (5.4) and fast.

The flow is tool-neutral — the FSM and patterns are reproducible in a free simulator. Real ATPG/coverage come from the ATPG tool. No paid tool required.

15. Interview Perspective

• Weak: "You run ATPG on the FSM and it makes test patterns."
• Good: "ATPG loads a state, captures a transition, and observes the next state to test the FSM's logic, then reports coverage."
• Senior: "On the full-scan FSM, ATPG runs combinationally (flops as pseudo-PI/PO): for a target fault it justifies the current state by loading it through the scan chain, sets inputs, propagates the effect to a scan cell, and emits a load-state/capture/observe pattern — e.g. load RUN, fin=1, capture → expect DONE; a faulty machine stays RUN → detected. It fault-simulates to drop, random-fills, and compacts for a small set, then classifies faults DT/RE/AU/AB. An undetected fault isn't 'ATPG failed' — it's aborted (raise effort), AU (add a test point), or redundant (accept), diagnosed via controllability/observability (5.2). The FSM being full scan is what made ATPG fast and high-coverage — and the classified report goes to signoff (Ch6)."

16. Interview / Review Questions

17. Key Takeaways

• Running ATPG on the full-scan FSM (4.5) is the concrete payoff of Chapters 2–5: fault models + scan access + ATPG → an applied, compact pattern set and a classified coverage report.
• Because the FSM is full scan, ATPG runs combinationally (5.4): it justifies any current state by loading it through the scan chain and propagates faults to scan cells, emitting load-state → capture → observe patterns.
• A functionally-unreachable next-state fault (e.g. RUN→DONE stuck) becomes a single pattern — load RUN, fin=1, capture, compare golden DONE — so a faulty die's RUN ≠ DONE → detected.
• The run uses fault-sim dropping, random-fill, and compaction (5.3) for a small set, and classifies faults DT/RE/AU/AB (5.5) — recover aborts, test-point AU, accept redundant.
• An undetected fault is a class, not a tool failure — diagnosed by controllability/observability (5.2) and classification (5.5); the classified coverage is the direct input to coverage closure (Chapter 6). Next: Chapter 6 — Coverage & Signoff (turning this report into a signed-off, DPPM-driven number).

18. Quick Revision

ATPG on the FSM (Ch5 capstone). Input: DRC-clean full-scan FSM (4.5) + stuck-at fault list (Ch2). Full scan → COMBINATIONAL ATPG (flops pseudo-PI/PO): per fault, JUSTIFY the current state by LOADING it + set inputs → PROPAGATE to a scan cell → emit a load-state/capture/observe pattern → fault-sim drop + random-fill + compact (5.3) → classify DT/RE/AU/AB (5.5). Concrete: load RUN, fin=1, capture → expect DONE; faulty stays RUN → DETECTED (the fault 4.5 couldn't reach functionally). Report: ~14 patterns, ~98-99% test coverage. Undetected = a CLASS (aborted→effort / AU→test point / redundant→accept), NOT a tool failure. Output → coverage closure (Ch6), STIL → ATE (1.3). Next: Chapter 6 — Coverage & Signoff.